ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 50

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
Table 34.
Table 35.
Table 36.
Table 37.
ISP1505A_ISP1505C_3
Product data sheet
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
-
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
USB Interrupt Status register (address R = 13h) bit description
USB Interrupt Latch register (address R = 14h) bit allocation
USB Interrupt Latch register (address R = 14h) bit description
Debug register (address R = 15h) bit allocation
Symbol
-
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
10.1.8 USB Interrupt Latch register
10.1.9 Debug register
R
R
7
0
7
0
The bits of the USB Interrupt Latch register are automatically set by the ISP1505 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1505 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
R
R
6
0
6
0
Description
reserved
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
Description
reserved
Session End: Reflects the current value of the session end voltage comparator.
Session Valid: Reflects the current value of the session valid voltage comparator.
V
Host Disconnect: Reflects the current value of the host disconnect detector.
reserved
BUS
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Valid: Reflects the current value of the V
R
R
5
0
5
0
Rev. 03 — 26 August 2008
reserved
R
R
4
0
4
0
ULPI HS USB host and peripheral transceiver
SESS_
END_L
Table
R
R
3
0
3
0
ISP1505A; ISP1505C
35.
Table
BUS
VALID_L
SESS_
valid voltage comparator.
37. This register indicates the
R
R
2
0
2
0
VALID_L
STATE1
VBUS_
LINE
R
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_L
STATE0
HOST_
LINE
R
R
0
0
0
0
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