ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 44

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
10. Register map
Table 17.
[1]
[2]
[3]
[4]
Table 18.
[1]
[2]
[3]
[4]
ISP1505A_ISP1505C_3
Product data sheet
Field name
Immediate register set
Vendor ID Low register
Vendor ID High register
Product ID Low register
Product ID High register
Function Control register
Interface Control register
OTG Control register
USB Interrupt Enable Rising Edge
register
USB Interrupt Enable Falling Edge
register
USB Interrupt Status register
USB Interrupt Latch register
Debug register
Scratch register
Reserved (do not use)
Access extended register set
Vendor-specific registers
Power Control register
Field name
Maps to immediate register set above 8
Reserved (do not use)
Read (R): A register can be read. Read-only if this is the only mode given.
Write (W): The pattern on the data bus will be written over all bits of a register.
Set (S): The pattern on the data bus is OR-ed with and written to a register.
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
Read (R): A register can be read. Read-only if this is the only mode given.
Write (W): The pattern on the data bus will be written over all bits of a register.
Set (S): The pattern on the data bus is OR-ed with and written to a register.
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
Immediate register set overview
Extended register set overview
Size
(bit)
8
8
8
8
8
8
8
8
8
8
8
8
8
-
8
8
8
Size
(bit)
8
Address (6 bit)
R
00h
01h
02h
03h
04h to 06h
07h to 09h
0Ah to 0Ch
0Dh to 0Fh
10h to 12h
13h
14h
15h
16h to 18h
-
Address (6 bit)
R
[1]
[1]
Rev. 03 — 26 August 2008
W
[2]
W
-
-
-
-
04h
07h
0Ah
0Dh
10h
-
-
-
16h
2Fh
3Dh to 3Fh
19h to 2Eh
30h to 3Ch
00h to 3Fh
40h to FFh
[2]
ULPI HS USB host and peripheral transceiver
S
[3]
S
-
-
-
-
05h
08h
0Bh
0Eh
11h
-
-
-
17h
-
[3]
ISP1505A; ISP1505C
C
[4]
C
-
-
-
-
06h
09h
0Ch
0Fh
12h
-
-
-
18h
-
[4]
References
Section 10.1.1 on page 44
Section 10.1.2 on page 44
Section 10.1.3 on page 45
Section 10.1.4 on page 46
Section 10.1.5 on page 47
Section 10.1.6 on page 48
Section 10.1.7 on page 48
Section 10.1.8 on page 49
Section 10.1.9 on page 49
Section 10.1.10 on page 50
Section 10.1.11 on page 50
Section 10.1.12 on page 50
Section 10.1.13 on page 50
Section 10.1.14 on page 50
References
Section 10.2 on page 51
© NXP B.V. 2008. All rights reserved.
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