FDMF6707B Fairchild Semiconductor, FDMF6707B Datasheet - Page 11

• Manufacturer Part Number: FDMF6707B
• Description: MOSFET & Power Driver ICs XS DrMOS; Hi-Freq Hi-Perf Module
• Manufacturer: Fairchild Semiconductor
• Type: Power MOSFETr

Specifications of FDMF6707B

• Product: MOSFET Gate Drivers
• Rise Time: 6 ns
• Fall Time: 5 ns
• Propagation Delay Time: 25 ns
• Supply Voltage (max): 15 V
• Supply Voltage (min): 3 V
• Package / Case: PQFN-40
• Number Of Drivers: 1
• Output Current: 50 A
• Output Voltage: 12 V
• Transistor Polarity: N-Channel
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2011 Fairchild Semiconductor Corporation
FDMF6707B • Rev. 1.0.1
THWN#
Logic
State
Functional Description
The FDMF6707B is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an under-voltage lockout
(UVLO) circuit. When V
is enabled for operation. When V
the driver is disabled (GH, GL=0). The driver can also
be disabled by pulling the DISB# pin LOW (DISB# <
V
of the PWM input state. The driver can be enabled by
raising the DISB# pin voltage HIGH (DISB# > V
Table 1.
Note:
2.
Thermal Warning Flag (THWN#)
The FDMF6707B provides a thermal warning flag
(THWN#) to advise of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
UVLO
IL_DISB
0
1
1
1
DISB# internal pull-down current source is 10µA.
), which holds both GL and GH LOW regardless
DISB#
HIGH
LOW
Open
UVLO and Disable Logic
Figure 24.
X
0
1
Normal
Operation
135°C Reset
Temperature
T
CIN
J_driver IC
THWN Operation
Enabled (See Table 2)
rises above ~3.1V, the driver
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Driver State
CIN
150°C
Activation
Temperature
falls below ~2.7V,
Thermal
Warning
IH_DISB
).
11
3-State PWM Input
The FDMF6707B incorporates a 3-state 3.3V PWM
input gate drive design. The 3-state gate drive has both
logic HIGH level and LOW level, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (t
LOW. This feature enables the gate drive to shut down
both high-and low-side MOSFETs to support features
such as phase shedding, a common feature on multi-
phase voltage regulators.
Exiting 3-State Condition
When exiting a valid 3-state condition, the FDMF6707B
design follows the PWM input command. If the PWM
input goes from 3-state to LOW, the low-side MOSFET
is turned on. If the PWM input goes from 3-state to
HIGH, the high-side MOSFET is turned on, as illustrated
in Figure 25. The FDMF6707B design allows for short
propagation delays when exiting the 3-state window (see
Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced low R
for GL is internally connected between VDRV and
CGND. When the driver is enabled, the driver's output is
180° out of phase with the PWM input. When the driver
is disabled (DISB#=0V), GL is held LOW.
High-Side Driver
The high-side driver is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (C
held at PGND, allowing C
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET (Q1). During this transition, the charge is
removed from C
As Q1 turns on, V
pin to V
enhancement for Q1. To complete the switching cycle,
Q1 is turned off by pulling GH to V
recharged to V
output is in-phase with the PWM input. The high-side
gate is held LOW when the driver is disabled or the
PWM signal is held within the 3-state window for
longer than the 3-state hold-off time, t
IN
+ V
D_HOLD-OFF
DRV
BOOT
BOOT
DS(ON)
SWH
when V
, which provides sufficient V
and delivered to the gate of Q1.
BOOT
rises to V
N-channel MOSFET. The bias
), both GL and GH are pulled
). During startup, V
BOOT
SWH
IN
falls to PGND. GH
to charge to V
, forcing the BOOT
SWH
D_HOLD-OFF
. C
BOOT
www.fairchildsemi.com
.
is then
SWH
DRV
GS
is