MT47H512M8WTR-3:C Micron Technology Inc, MT47H512M8WTR-3:C Datasheet - Page 11

• Manufacturer Part Number: MT47H512M8WTR-3:C
• Description: IC DDR2 SDRAM 4GBIT 63FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H512M8WTR-3:C

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 63-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 7: DDR2 I
Notes: 1–8 apply to the entire table
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. H 04/11 EN
Parameter/Condition
Operating burst read current: All banks open, continu-
ous burst reads, Iout = 0mA; BL = 4, CL = CL (I
t
is HIGH, CS# is HIGH between valid commands; address
bus
Burst refresh current:
at every
tween valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching (inac-
tive die is in I
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Oth-
er control and address bus inputs are floating; Data bus
inputs are floating
Operating bank interleave read current: All bank in-
terleaving reads, Iout = 0mA; BL = 4, CL = CL (I
t
t
HIGH between valid commands; address bus inputs are sta-
ble during deselects; Data bus inputs are switching (inac-
tive die is in I
CK =
RCD (I
RRD =
DD2P
t
CK (I
DD
t
RRD (I
t
condition, but with inputs switching)
) - 1 x
RFC(I
DD
DD2P
DD2P
),
DD
DD
t
t
CK (I
RAS =
),
) interval; CKE is HIGH, CS# is HIGH be-
condition, but with inputs switching)
condition, but with inputs switching)
DD
t
RCD =
DD
Specifications and Conditions (Die Revision A) (Continued)
Notes:
t
);
RAS MAX (I
t
CK =
t
CK =
t
RCD (Idd); CKE is HIGH, CS# is
t
CK (I
t
1. I
2. I
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. Idd values must be met
4. I
5. Definitions for I
6. I
7. I
8. The following I
CK (I
V
with all combinations of EMR bits 10 and 11.
die values.
tion devices when operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
DD
CDD
CDD
CDD
DD1
CDD
DD
DD
DD
),
); refresh command
, I
/I
/I
/I
),
= V
values reflect the combined current of both individual die. I
t
DD
DD
DD
RP =
DD4R
t
RC =
values must be met with all combinations of EMR bits 10 and 11.
DDQ
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, and I
t
RP (I
DD
t
= +1.8V ±0.1V; V
DD
RC (I
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
), AL = 0;
IN(AC)
IN
), AL =
DD
DD
CDD
DD7
≥ V
DD
); CKE
values must be derated (I
/I
),
≤ V
IH(AC)min
require A12 in EMR1 to be enabled during testing.
DD
IL(AC)max
conditions:
REF
11
= V
Symbol
Electrical Specifications – I
bined
Com-
I
DDL
I
I
I
CDD4R
CDD5
CDD6
CDD7
DDQ
= +1.8V ±0.1V; V
/2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Die Status
Individual
4Gb: x4, x8 TwinDie DDR2 SDRAM
I
I
I
DD6
I
DD4R
I
DD5
DD7
I
I
I
CDD4R
CDD5
CDD6
CDD7
DD
+ I
+ 13
+ 13
+ 13
DD6
=
=
=
limits increase) on IT-option or on AT-op-
=
REF
Width
= V
x4, x8
x4, x8
x4, x8
x4, x8
Bus
DDQ
C
≤ 85°C:
/2.
© 2006 Micron Technology, Inc. All rights reserved.
-25
203
313
403
20
DDx
CDD
-3E/-3
represents individual
183
293
353
20
Parameters
-37E Units
163
273
308
20
C
≤ +85°C.
mA
mA
mA
mA