MT47H512M8WTR-3:C Micron Technology Inc, MT47H512M8WTR-3:C Datasheet - Page 13

• Manufacturer Part Number: MT47H512M8WTR-3:C
• Description: IC DDR2 SDRAM 4GBIT 63FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H512M8WTR-3:C

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 63-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 8: DDR2 I
Notes: 1–8 apply to the entire table
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. H 04/11 EN
Parameter/Condition
Operating burst read current: All banks open, continuous
burst reads, Iout = 0mA; BL = 4, CL = CL (I
(I
is HIGH between valid commands; address bus inputs are
switching; Data bus inputs are switching (inactive die is in
I
Burst refresh current:
every
id commands; Other control and address bus inputs are switch-
ing; Data bus inputs are switching (inactive die is in I
condition, but with inputs switching)
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
Operating bank interleave read current: All bank inter-
leaving reads, Iout = 0mA; BL = 4, CL = CL (I
(I
(I
id commands; address bus inputs are stable during deselects;
Data bus inputs are switching (inactive die is in I
tion, but with inputs switching)
DD2P
DD
DD
DD
),
) - 1 x
),
condition, but with inputs switching)
t
t
t
RAS =
RCD =
RFC(I
t
CK (I
DD
t
t
RAS MAX (I
RCD (Idd); CKE is HIGH, CS# is HIGH between val-
) interval; CKE is HIGH, CS# is HIGH between val-
DD
);
DD
t
CK =
Specifications and Conditions (Die Revision C) (Continued)
Notes:
t
CK =
DD
t
CK (I
),
t
RP =
t
CK (I
DD
1. I
2. I
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. Idd values must be met
4. I
5. Definitions for I
6. I
7. I
8. The following I
),
V
with all combinations of EMR bits 10 and 11.
die values.
tion devices when operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
t
CDD
CDD
CDD
DD1
CDD
t
DD
RP (I
RC =
DD
); refresh command at
, I
/I
/I
/I
= V
values reflect the combined current of both individual die. I
DD
DD
DD
DD4R
DD
t
RC (I
DD
values must be met with all combinations of EMR bits 10 and 11.
DDQ
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
); CKE is HIGH, CS#
DD
), AL = 0;
, and I
), AL =
DD
= +1.8V ±0.1V; V
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
IN(AC)
IN
),
DD2P
DD
CDD
t
DD7
≥ V
RRD =
values must be derated (I
DD2P
t
t
condi-
/I
RCD
≤ V
IH(AC)min
CK =
require A12 in EMR1 to be enabled during testing.
DD
IL(AC)max
t
conditions:
REF
RRD
t
CK
13
= V
Electrical Specifications – I
DDL
Combined
DDQ
Symbol
= +1.8V ±0.1V; V
I
I
I
I
CDD4R
CDD5
CDD6
CDD7
/2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4Gb: x4, x8 TwinDie DDR2 SDRAM
I
DD
I
I
DD4R
Die Status
Individual
DD5
DD7
I
DD6
I
limits increase) on IT-option or on AT-op-
I
I
I
CDD4R
CDD5
CDD6
CDD7
+ I
+ I
+ I
REF
+ I
CDD2P
CDD2P
CDD2P
DD6
=
=
=
= V
=
DDQ
C
≤ 85°C:
Width
/2.
x4, x8
x4, x8
x4, x8
x4, x8
Bus
© 2006 Micron Technology, Inc. All rights reserved.
DDx
CDD
represents individual
162
197
262
-25
24
Parameters
-3E/-3 Units
142
177
237
24
C
≤ +85°C.
mA
mA
mA
mA