PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 20

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

• Support of automatic protection switching
• Dual-rail or single-rail digital inputs and outputs
• Unipolar NRZ or CMI for interfacing fiber-optical transmission routes
• Selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS)
• Loss-of-signal indication with programmable thresholds according to ITU-T G.775,
• Optional data stream muting upon LOS detection
• Programmable receive slicer threshold
• Clock generator for jitter-free system/transmit clocks per channel
• Local loop and remote loop for diagnostic purposes
• Low power device, single power supply: 3.3 V with 5 V tolerant digital inputs
Frame Aligner
• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 (E1) and for
• Programmable frame formats:
• Selectable conditions for recover/loss of frame alignment
• CRC4 to non-CRC4 interworking according to ITU-T G. 706 Annex B (E1)
• Error checking via CRC4 procedures according to ITU-T G. 706 (E1)
• Error checking via CRC6 procedures according to ITU-T G. 706 and JT G.706 (T1/J1)
• Performs synchronization in ESF format according to NTT requirements (J1)
• Alarm and performance monitoring per second
• Insertion and extraction of alarm indication signals (AIS, remote/yellow alarm,…)
• Remote alarm generation/checking according to ITU JT-G.704 in ESF-format (J1)
• IDLE code insertion for selectable channels
• Single-bit defect insertion
• Flexible system clock frequency for receiver and transmitter
• Supports programmable system data rates with independent receive/transmit shifts:
• Elastic store for receive and transmit route clock wander and jitter compensation;
• Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
• Provides different time slot mapping modes
• Supports fractional E1 or T1/J1 access
• Flexible transparent modes
• Programmable in-band loop code detection and generation (TR62411)
Data Sheet
ETS300233 (E1) and ANSI T1.403 (T1/J1)
1544 kbit/s according to ITU-T G.704 and JT G.704 (T1/J1)
E1: Doubleframe, CRC multiframe (E1)
T1: 4-frame multiframe (F4,FT), 12-frame multiframe (F12, D3/4), extended
superframe (F24, ESF), remote switch mode (F72, SLC96)
16 bit counter for CRC-errors, framing errors, code violations, error monitoring via
E-bit and SA6-bit (E1), errored blocks, PRBS bit errors
E1: 2.048, 4.096, 8.192 and 16.384 Mbit/s (according to H.100/H.110 bus)
T1/J1: 2.048, 4.096, 8.192, 16.384 Mbit/s and 1.544, 3.088, 6.176, 12.352 Mbit/s
controlled slip capability and slip indication
20
FALC56 V1.2
Introduction
PEB 2256
2002-08-27