PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 435

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

RFS2
RDO2
ALLS2
XDU2
RPF2
Data Sheet
Receive Frame Start - HDLC Channel 2
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an
RFS2 interrupt, the contents of
• RAL1
• RSIS2 bits 3 to 1
are valid and can be read by the CPU.
Receive Data Overflow - HDLC Channel 2
This interrupt status indicates that the CPU did not respond fast
enough to an RPF2 or RME2 interrupt and that data in RFIFO2 has
been lost. Even when this interrupt status is generated, the frame
continues to be received when space in the RFIFO2 is available
again.
Note: Whereas the bit RSIS2.RDO2 in the frame status byte
All Sent - HDLC Channel 2
This bit is set if the last bit of the current frame has been sent
completely and XFIFO2 is empty. This bit is valid in HDLC mode only.
Transmit Data Underrun - HDLC Channel 2
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO2 and no XME2 was
issued.
Note: Transmitter and XFIFO2 are reset and deactivated if this
Receive Pool Full - HDLC Channel 2
32 bytes of a frame have arrived in the receive FIFO2. The frame is
not yet completely received.
indicates whether an overflow occurred when receiving the
frame currently accessed in the RFIFO2, the ISR4.RDO2
interrupt status is generated as soon as an overflow occurs
and does not necessarily pertain to the frame currently
accessed by the processor.
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU2 should not be
masked via register IMR4.
435
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27