PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 270

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XTF2
XME2
SRES2
Command Register 4 (Write)
Value after reset: 00
CMDR4
RMC3
XREP3
XHF3
Data Sheet
RMC3
7
Transmit Transparent Frame - HDLC Channel 2
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End - HDLC Channel 2
Indicates that the data block written last to the XFIFO2 completes the
current frame. The FALC
properly by appending the CRC and the closing flag sequence to the
data.
Signaling Transmitter Reset - HDLC Channel 2
The transmitter of the signaling controller is reset. XFIFO2 is cleared
of any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to SRES2 an XPR2 interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Receive Message Complete - HDLC Channel 3
Confirmation from CPU to FALC
has been fetched following an RPF3 or RME3 interrupt, thus the
occupied space in the RFIFO3 can be released.
Transmission Repeat - HDLC Channel 3
If XREP3 is set together with XTF3 (write 24H to CMDR4), the FALC
repeatedly transmits the contents of the XFIFO3 (1 to 32 bytes)
without HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES3 command or by
resetting XREP3.
Transmit HDLC Frame - HDLC Channel 3
After having written up to 32 bytes to the XFIFO3, this command
initiates the transmission of a HDLC frame.
H
XREP3
270
®
XHF3
can terminate the transmission operation
®
that the current frame or data block
XTF3
XME3
SRES3
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(89)
®