PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 341

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Common Configuration Register 2 (Read/Write)
Value after reset: 00
CCR2
Unused bits have to be cleared.
RADD
RBFE
RCRC
XCRC
Data Sheet
7
Receive Address Pushed to RFIFO - HDLC Channel 1
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected by MODE.MDS0) is pushed
to RFIFO. This function is applicable in non-auto mode and
transparent mode 1. RADD must be set, if SS7 mode is selected.
Receive BOM Filter Enable - HDLC Channel 1
Setting this bit the bit oriented message (BOM) receiver only accepts
BOM frames after detecting 7 out of 10 equal BOM pattern. The BOM
pattern is stored in the RFIFO adding a receive status byte marking a
BOM frame (RSIS.HFR) and an interrupt ISR0.RME is generated.
The current state of the BOM receiver is indicated in register SIS.IVB.
When the valid BOM pattern disappears an interrupt ISR0.BIV is
generated.
Receive CRC on/off - HDLC Channel 1
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO by the status information
byte (contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “valid frame” check are modified (refer to RSIS.VFR).
Transmit CRC on/off - HDLC Channel 1
If this bit is set, the CRC checksum is not generated internally. It has
to be written as the last two bytes in the transmit FIFO (XFIFO). The
transmitted frame is closed automatically with a closing flag.
Note: The FALC56 does not check whether the length of the frame,
H
i.e., the number of bytes to be transmitted, makes sense or
not.
RADD
341
RBFE
RCRC
XCRC
T1/J1 Registers
FALC56 V1.2
0
PEB 2256
2002-08-27
(0A)