M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet - Page 17

• Manufacturer Part Number: M25P10-AVMN6TP
• Manufacturer: Micron Technology Inc

Specifications of M25P10-AVMN6TP

• Lead Free Status / Rohs Status: Compliant

Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
Note: 1. Address bits A23 to A17 are Don’t Care.
Read Data Bytes (READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency f
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location.
The address is automatically incremented to the
S
C
D
Q
0
1
High Impedance
R
2
Instruction
, during the falling edge of
3
4
5
6
7
MSB
23
8
22 21
9 10
24-Bit Address
3
28 29 30 31 32 33 34 35
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
2
1
0
MSB
7
6
5
Data Out 1
4
3
36 37 38
2
1
0
39
7
Data Out 2
AI03748D
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