M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet - Page 21

• Manufacturer Part Number: M25P10-AVMN6TP
• Manufacturer: Micron Technology Inc

Specifications of M25P10-AVMN6TP

• Lead Free Status / Rohs Status: Compliant

Figure 16. Bulk Erase (BE) Instruction Sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
S
C
D
0
1
2
Instruction
3
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Erase cycle (whose duration is
t
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
both Block Protect (BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more,
sectors are protected.
4
BE
5
) is initiated. While the Bulk Erase cycle is in
6
7
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