M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet - Page 9

• Manufacturer Part Number: M25P10-AVMN6TP
• Manufacturer: Micron Technology Inc

Specifications of M25P10-AVMN6TP

• Lead Free Status / Rohs Status: Compliant

Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P10-A boasts
the following data protection mechanisms:
Table 2. Protected Area Sizes
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
BP1 Bit
Power-On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
– Power-up
– Write Disable (WRDI) instruction completion
Status Register
0
0
1
1
Content
BP0 Bit
0
1
0
1
none
Upper quarter (Sector 3)
Upper half (two sectors: 2 and 3)
All sectors (four sectors: 0, 1, 2 and 3)
Protected Area
PUW
)
Memory Content
– Write Status Register (WRSR) instruction
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation
with the Status Register Write Disable (SRWD)
bit, allows the Block Protect (BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be
write-protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
completion
All sectors
Lower three-quarters (three sectors: 0 to 2)
Lower half (Sectors 0 and 1)
none
1
(four sectors: 0, 1, 2 and 3)
Unprotected Area
M25P10-A
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