M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet - Page 7

• Manufacturer Part Number: M25P10-AVMN6TP
• Manufacturer: Micron Technology Inc

Specifications of M25P10-AVMN6TP

• Lead Free Status / Rohs Status: Compliant

SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
Figure 4. Bus Master and Memory Devices on the SPI Bus
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL
0
1
SPI Interface with
(CPOL, CPHA) =
CS3
CPHA
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
0
1
Bus Master
CS2
D
Q
C
C
CS1
SDO
SDI
SCK
MSB
S
SPI Memory
C Q D
Device
W
HOLD
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
S
SPI Memory
C Q D
Device
W
MSB
HOLD
S
SPI Memory
C Q D
Device
W
AI03746D
M25P10-A
HOLD
AI01438B
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