ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 65

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

SYNC PROCESSOR (SYNC) (Cont’d)
4.4.8 Analyzer Mode
The analyzer block is used for all extra
measurements on the sync signals to manage the
monitor functions:
– Measure the number of scan lines per frame
– Measure the low level of HSYNCO or HFBACK.
This function can be used for VSYNCO pulse
extension or for a fast estimation of the incoming
Hsync signal period.
– Detection of the pre/post equalization pulses.
Notes:
1. Analyzer mode should be performed before
2. When analyzer mode is active, the free-running
3. If H/VBACK are selected (FBSEL=0) corrector
4. For all measurements, HSYNCO and VSYNCO
4.4.8.1 Horizontal Low Level Measurement
The measurement starts in setting HACQ by
software. When this bit is cleared by hardware, the
HGENR register returns the result.
The algorithm is shown in
HLow = ((255-HGENR+1)/4) µs
Note: HLow maximum value = 64µs (even if real value is
(VSYNCO or VFBACK) to simplify the OSD ver-
tical centering.
corrector mode.
frequencies generator and corrector mode must
be disabled.
– HVGEN = 0 in ENR register
– 2FHINH 0 in CFGR register for Horizontal low
– VEXT = 0, VCORDIS = 1 in CFGR, POLR reg-
mode must be disabled
must be POSITIVE.
level measurement
isters for Vertical output measurement
greater)
Figure
45.
For maximum accuracy, it is possible to measure
the low level of HFBACK with the same technique
(FBSEL bit in the MCR register).
Figure 45. Horizontal Low Level Measurement
No
Select H/VBACK or H/VSYNCO
Disable H internal generation
HSYNCO Positive polarity
Disable H correction Mode
Start measurement
HGENR=Result
Measure HLow
FBSEL=0 or 1
HACQ=0?
HVGEN=0
ST72774/ST727754/ST72734
2FHINH=0
HACQ=1
END
Yes
Necessary if Signals
are H/VSYNCO
VR02118A
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