ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 83

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

USB INTERFACE (Cont’d)
ENDPOINT n REGISTER A (EPnRA)
Read / Write
Reset Value: 0000 xxxx (0xh)
These registers (EP0RA, EP1RA and EP2RA) are
used for controlling data transmission. They are
also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RA register are not availa-
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status
out packet is expected: in this case, all nonzero
OUT data transfers on the endpoint are STALLed
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes,
as needed.
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the
reception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from
DTOG_RX (see EPnRB) are normally updated by
hardware, at the receipt of a relevant PID. They
can be also written by software.
OUT
ST_
7
ble on some devices (see device feature list and
register map).
the
DTOG
_TX
USB
STAT
_TX1
host.
STAT
_TX0
DTOG_TX
TBC
3
TBC
2
TBC
and
1
TBC
also
0
0
Bits 5:4 = STAT_TX[1:0] Status bits, for
transmission transfers.
These bits contain the information about the
endpoint status, which are listed below:
These bits are written by software. Hardware sets
the STAT_TX bits to NAK when a correct transfer
has occurred (CTR=1) related to a IN or SETUP
transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
transmitted.
Bits 3:0 = TBC[3:0] Transmit byte count for
Endpoint n.
Before transmission, after filling the transmit
buffer, software must write in the TBC field the
transmit packet size expressed in bytes (in the
range 0-8).
STAT_TX1 STAT_TX0 Meaning
0
0
1
1
0
1
0
1
ST72774/ST727754/ST72734
DISABLED: transmission
transfers cannot be execut-
ed.
STALL: the endpoint is
stalled and all transmission
requests result in a STALL
handshake.
NAK: the endpoint is naked
and all transmission re-
quests result in a NAK hand-
shake.
VALID: this endpoint is ena-
bled for transmission.
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