UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 112

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(3) 16-bit capture/compare register 010, 011 (CR010, CR011)
6.4 Registers Controlling 16-Bit Timer/Event Counter
(1) 16-bit timer mode control register 00, 01 (TMC00, TMC01)
110
The following nine types of registers are used to control 16-bit timer/event counters 00 and 01.
• 16-bit timer mode control register 00, 01 (TMC00, TMC01)
• Capture/compare control register 00, 01 (CRC00, CRC01)
• Timer output control register 00, 01 (TOC00, TOC01)
• Prescaler mode register 00, 01 (PRM00, PRM01)
• Port mode register 5 (PM5)
• When CR01n is used as a compare register
• When CR01n is used as a capture register
Caution
Caution
CR010 and CR011 are 16-bit registers that have the functions of both a capture register and a compare register.
Whether to be used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control
register 0n (CRC0n).
CR01n is set by a 16-bit memory manipulation instruction.
RESET input makes the value of CR01n undefined.
Remark n = 0, 1
These registers set the 16-bit timer operating mode, 16-bit timer counter 00, 01 (TM00, TM01) clear mode, and
output timing, and detect an overflow.
TMC00 and TMC01 are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC00 and TMC01 to 00H.
The value set in CR01n is constantly compared with the 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM01n) is generated if they match.
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n valid edge is set by
means of prescaler mode register 0n (PRM0n).
In the clear & start mode entered on a match between TM0n and CR00n, set CR01n to a value
other than 0000H. However, in the free-running mode and the clear mode of the valid edge
of TI00n, if CR01n is set to 0000H, an interrupt request (INTTM01n) is generated after the
overflow (FFFFH).
16-bit timer counter 0n (TM0n) starts operating the instant that TMC0n2 and TMC0n3 (n = 0,
1) are set to a value other than 0 (operation stop mode). To stop operation, set TMC0n2 and
TMC0n3 to 0.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
User’s Manual U13029EJ7V1UD