UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 347

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

19.2 Operation List
8-bit data
transfer
Instruction
Group
Notes 1. When the internal high-speed RAM area is accessed or when an instruction that does not access data
Remarks 1. One clock of an instruction is equal to one CPU clock (f
2. When an area other than the internal high-speed RAM area is accessed
3. Except r = A
Mnemonic
MOV
2. The number of clocks shown is when the program is stored in the internal ROM area.
3. n indicates the number of wait states when the external memory expansion area is read.
4. m indicates the number of wait states when the external memory expansion area is written.
is executed
register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
Operand
Note 3
Note 3
CHAPTER 19 INSTRUCTION SET
User’s Manual U13029EJ7V1UD
Byte
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
Note 1 Note 2
4
6
–
2
2
4
4
–
–
8
8
–
–
–
4
4
4
4
8
8
6
6
6
6
Clock
9 + m
5 + m
5 + m
9 + m
7 + m
7 + m
9 + n
5 + n
9 + n
7 + n
5 + n
7 + n
–
7
7
–
–
5
5
5
5
7
5
5
r
(saddr)
sfr
A
r
A
(saddr)
A
sfr
A
(addr16)
PSW
A
PSW
A
(DE)
A
(HL)
A
(HL + byte)
A
(HL + B)
A
(HL + C)
byte
A
r
(saddr)
sfr
(addr16)
PSW
(DE)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
A
CPU
A
A
byte
A
) selected by the processor clock control
byte
A
A
A
A
A
Operation
Z AC CY
Flag
345