UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 299

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Maskable interrupt request
Non-maskable interrupt request
RESET input
: don’t care
(c) Releasing by RESET input
Releasing Source
If the RESET signal is input, the HALT mode is released. After branching to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started again.
Remarks 1. f
RESET
signal
Clock
2. The parenthesized values apply to operation at f
Operation
mode
X
: System clock oscillation frequency
Figure 16-3. Releasing HALT Mode by RESET Input
instruction
Table 16-2. Operation After Release of HALT Mode
HALT
MK
0
0
0
0
0
1
–
–
CHAPTER 16 STANDBY FUNCTION
HALT mode
Oscillation
User’s Manual U13029EJ7V1UD
PR
0
0
1
1
1
–
–
Oscillation
IE
0
1
0
1
period
Reset
stops
ISP
1
0
1
(2
17
stabilization
Oscillation
wait status
Oscillation
/f
X
X
Wait
Executes next address instruction.
Executes interrupt servicing.
Executes next address instruction.
Executes interrupt servicing.
Retains HALT mode.
Executes interrupt servicing.
Executes reset processing.
: 10.9 ms)
= 12 MHz.
Operation
Operation
mode
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