UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 138

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(6) Operation of OVF0n flag
(7) Conflicting Operations
136
<1> The OVF0n flag (bit 6 of 16-bit timer mode control register 0n (TMC0n)) is set to 1 the next time.
<2> After TM0n overflows, it is reset and the clear instruction becomes invalid even though the OVF0n flag is
<1> Conflicting operations between the read time of 16-bit capture/compare register 00n, 01n (CR00n,
<2> Match timing of conflicting operations between the write period of 16-bit capture/compare register
Remark n = 0, 1
Remark n = 0, 1
Remark n = 0, 1
Remark n = 0, 1
One of clear & start mode entered on match between TM0n and CR00n, clear & start mode entered at the
valid edge of TI00n, and free-running mode is selected.
When TM0n is counted up from FFFFH to 0000H.
cleared before the next count clock (before TM0n becomes 0001H).
CR01n) and capture trigger input (CR00n and CR01n used as capture register)
Capture trigger input has priority. The data read from CR00n and CR01n is undefined.
00n, 01n (CR00n, CR01n) and 16-bit timer counter 0n (TM0n) (CR00n and CR01n used as compare
register)
Match judgement is not performed normally. Do not write any data to CR00n and CR01n near the match
timing.
CR00n is set to FFFFH.
Count clock
INTTM00n
OVF0n
CR00n
TM0n
Figure 6-36. Operation Timing of OVF0n Flag
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
FFFEH
FFFFH
User’s Manual U13029EJ7V1UD
FFFFH
0000H
0001H