DA82562EM Intel, DA82562EM Datasheet - Page 133

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
100BASE-TX Receive Error Frame Counter: Register 21
Receive Symbol Error Counter: Register 22
100BASE-TX Receive EOF Error Counter: Register 23
10BASE-T Receive EOF Error Counter: Register 24
10BASE-T Transmit Jabber Detect Counter: Register 25
Bit
15:0
Bit
15:0
Bit
15:0
Bit
15:0
Bit
15:0
Name
Receive Error Frame
Name
Symbol Error
Name
Premature End of Frame
Name
End of Frame
Name
Jabber Detect
R / W
RO
SC
R / W
RO
SC
R / W
RO
SC
R / W
RO
SC
R / W
RO
SC
Description
This register contains a 16-bit counter for receive
error frames. It is incremented for frames with a
receive error condition (frames containing a symbol
error or frames with a premature end of frame).
When the counter is full, additional error frames are
not counted. This counter is self-clearing on read.
Description
This register contains a 16-bit counter and
increments for each symbol error. The counter stop
counting additional symbol errors when it is full.
This counter is self-clearing on read.
Description
This register contains a 16-bit counter and
increments for each premature end of frame event.
It stops counting additional premature end of frame
events when it is full. It is self-clearing on read.
Description
This register is a 16-bit counter that increments for
each end of frame error event. The counter stops
counting additional errors when it is full. It is self-
clearing on read.
Description
This register is a 16-bit counter that increments for
each jabber detection event. The counter stops
counting additional events when it is full. It is self-
clearing on read.
Physical Layer Interface
Default
0
Default
0
Default
0
Default
0
Default
0
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