DA82562EM Intel, DA82562EM Datasheet - Page 87

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
The first 8 bytes of the configuration are kept by the CU, and the remainder are transferred by the
transmit DMA to the execution machine. When a configuration command is received, the CU
performs the following sequence:
1. Begins execution of the configuration action command.
2. Reads the first eight configure bytes and saves their content.
3. Writes the configure command to the transmit FIFO.
4. Initiates the transmit DMA to transfer the remainder of the configure bytes, up to the specified
5. Waits for the execution machine to complete its internal update of configuration registers.
6. Prepares the status word with C = 1 and OK = 1.
7. Completes the configuration action command.
•
•
BYTE 20.
BYTE 21.
byte count, to the execution machine.
— Bit 0 - Address Wake-up (82558 A-step); IA Match Wake Enable (82558 B-step). This bit
— Bit 6 - Multiple IA. When this bit is set, it enables the device to receive multiple IA
— Bit 5: Priority FC Location. This bit is reserved on the 82557 and should be set to 01.
— Bit 3 - Multicast All. This bit enables the device to receive all frames with a multicast
Recommended - 0.
is reserved on the 82557 and 82559 and should be set to 0 on those devices.
When this bit is set on the 82558 A-step, it enables assertion of the INTA# signal as a
special wake-up signal upon reception of a frame that passes any of device address
filtering mechanisms (according to the configuration of broadcast, promiscuous, IA,
multicast all or multiple IA). This bit takes effect only if the wake enable bit is set in the
PMCSR.
For the 82558 B-Step, this bit has a similar but slightly different function. On the 82558
B-step, it enables the assertion of the PME# signal upon reception of packets that pass the
individual address filtering. The PME# signal is further gated by the PME enable bit in the
PMCSR.
Default - 0 (off; 82557 compatible).
Recommended - 0.
frames using the HASH mechanism. If it is disabled, HASH will only be used for
multicast frames (odd address number).
Default - 0 (disabled).
Recommended - 0.
For the 82558 and 82559, this bit determines the location of the priority field in the flow
control frame. When it equals 0, the priority field is in byte #19 (after the time filed).
When it is 1, the priority field is in byte #31 (12 bytes later).
0 = Priority field in byte #19.
1 = Priority field in byte #31.
Default - 1.
address (1 in the least significant byte - odd address).
Default - 0 (disabled).
Recommended - 0.
Host Software Interface
79