DA82562EM Intel, DA82562EM Datasheet - Page 64

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Host Software Interface
6.3.11
56
Table 32. General Control Register Location
Table 33. General Control Register
Table 34. General Status Register Location
Table 35. General Status Register
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
General Status Register
The General Status register provides some basic status information in the 82559. It is an 8-bit entity
at offset 1Dh of the CSR. This register is only present in the 82559 and is not valid for the 82558 or
82557.
Bits
7:2
1
0
Bits
7:3
PMDR
PMDR
EEPROM Control Register
Upper Word (D31:D16)
Upper Word (D31:D16)
Operation
R
R/W
R/W
Operation
R
SCB Command Word
Early Receive Interrupt Receive Byte Count Register
Early Receive Interrupt Receive Byte Count Register
Reserved
Reserved
Default
PCI Reset
0
0
0
Default
0
FC Xon/Xoff
FC Xon/Xoff
SCB General Pointer
MDI Control Register
Description
Reserved.
Deep Power Down on Link Down. When this bit is 1, the 82559 may
enter a deep power down state (sub 7 mA) in the D2 and D3 power
states while the link is down. At this state, the 82559 does not maintain
link integrity. It is not supported for point to point connection of two end
stations.
Clockrun Disable. When this bit is 1, the 82559 always requests the PCI
CLK. This mode can be used to overcome potential receive overruns
caused by a very long system CLKRUN latency.
Description
Reserved.
PORT
SCB Status Word
General Status
General Status
FC Threshold
FC Threshold
Lower Word (D15:D0)
Lower Word (D15:D0)
Reserved
General Control
General Control
Early Rx Int
Early Rx Int
Base + 1Ch
Base + 1Ch
Base + 14h
Base + 18h
Base + 10h
Base + 14h
Base + 18h
Base + 0h
Base + 4h
Base + 8h
Base + Ch
Offset
Offset