DA82562EM Intel, DA82562EM Datasheet - Page 161

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

82550 and 82551 Specific Information B
B.1
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 66. IPCB Structure
Table 67. IP Activation Bits (Byte 13)
Table 68. IP Activation Bits (Byte 12)
This appendix applies to the Intel
IPCB
The IP command block (IPCB) is new and used to activate the new offloading features of the
82550 and 82551. The value of the command field for IPCB is 9h. The relevant aspects of the
IPCB for each feature is described in the following subsections. This section summarizes the most
useful combinations of the IPCB fields.
NOTE: Source address insertion is not allowed when IPCB is used. Thus, the no source address insertion
The location and definition of the IPCB fields are summarized in the following table.
E
L
0
Large Send
TCP Header Offset (8 bits)
S
15
7
TBD Number
I
(NSAI) bit of the configure command must be 1.
IP Activation (12 bits)
CID (5 bits)
Total TCP Payload (16 bits)
0
TCP/UDP
Number
Odd Word (D31:D16)
Maximum TCP Payload
14
6
0
TCP/UDP
Checksum
IP Header Offset (8 bits)
000
Transmit Threshold
13
5
®
N
C
Transmit Buffer #0 Address (32 bits)
82550 and 82551 devices.
CMD = 1001
TBD Array Address (32 bits)
Scheduled
Send
IP
Checksum
Link Address (32 bits)
Reserved (32 bits)
12
4
C X O
E
O
F
E
L
Reserved
X
0
0
K
11
3
U
Activation (20 bits)
Even Word (D15:D0)
Transmit Buffer #0 Size (14 bits)
Reserved
X
IPCB Byte Count (14 bits)
VLAN (16 bits)
XXXX XXXX XXXX (12 bits)
10
Reserved (14 bits)
2
Insert
VLAN
X
9
1
Hardware
Parse
X
8
0
153
Offset
1Ch
10h
14h
18h
Ch
0h
4h
8h