MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 371

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

D.6.15 QSPI Status Register
SPSR — QSPI Status Register
SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
Bit 4 — Not Implemented
CPTQP[3:0] — Completed Queue Pointer
D.6.16 Receive Data RAM
RR[0:F] — Receive Data RAM
MC68336/376
USER’S MANUAL
15
RESET:
SPSR contains information concerning the current serial transmission. Only the QSPI
can set bits in SPSR. The CPU32 reads SPSR to obtain QSPI status information and
writes it to clear status flags.
SPIF is set after execution of the command at the address in ENDQP[3:0].
The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS
input pin is negated by an external driver.
HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit.
CPTQP[3:0] points to the last command executed. It is updated when the current com-
mand is complete. When the first command in a queue is executing, CPTQP[3:0] con-
tains either the reset value $0 or a pointer to the last command completed in the
previous queue.
Data received by the QSPI is stored in this segment. The CPU32 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the
individual queue entry. Receive RAM data can be accessed using byte, word, or long-
word addressing.
0 = QSPI is not finished.
1 = QSPI is finished.
0 = Normal operation.
1 = Another SPI node requested to become the network SPI master while the QSPI
0 = QSPI is not halted.
1 = QSPI is halted.
14
was enabled in master mode (SS input taken low).
13
12
SPCR3
11
10
REGISTER SUMMARY
9
8
SPIF
7
0
MODF
6
0
HALTA
5
0
4
0
0
$YFFD00 – $YFFD0E
3
0
CPTQP[3:0]
2
0
$YFFC1F
MOTOROLA
1
0
D-53
0
0