MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 85

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

MC68336/376
USER’S MANUAL
When the clock synthesizer is used, SYNCR determines the system clock frequency
and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. When the W or
Y values change, VCO frequency changes, and there is a VCO relock delay. The SYN-
CR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When
X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency
is one-fourth the VCO frequency (f
and system clock frequency is one-half the VCO frequency (f
delay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
The reset state of SYNCR ($3F00) results in a power-on f
is 4.194 MHz.
For the device to operate correctly, the clock frequency selected by the W, X, and Y
bits must be within the limits specified for the MCU.
Internal VCO frequency is determined by the following equations:
Table 5-2 shows clock control multipliers for all possible combinations of SYNCR bits.
To obtain clock frequency, find counter modulus in the leftmost column, then multiply
the reference frequency by the value in the appropriate prescaler cell. Shaded cells
exceed the maximum system clock frequency at the time of manual publication; how-
ever, they may be usable in the future. Refer to APPENDIX A ELECTRICAL CHAR-
ACTERISTICS for maximum allowable clock rate.
Table 5-3 shows clock frequencies available with a 4.194 MHz reference and a max-
imum specified clock frequency of 20.97 MHz. To obtain clock frequency, find counter
modulus in the leftmost column, then refer to appropriate prescaler cell. Shaded cells
exceed the maximum system clock frequency at the time of manual publication; how-
ever, they may be usable in the future. Refer to APPENDIX A ELECTRICAL CHAR-
ACTERISTICS for maximum system frequency (f
SYSTEM INTEGRATION MODULE
f
sys
=
f
f
VCO
VCO
VCO
--------- - 4 Y
128
f
ref
). When X = 1, a divide-by-two circuit is enabled
=
=
4f
2f
or
sys
sys
+
1
if X = 0
if X = 1
sys
2
2W
).
+
X
sys
VCO
of 8.388 MHz when f
). There is no relock
MOTOROLA
5-7
ref