MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 420

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

CSBAR D-17
CSBARBT D-17
CSBOOT 5-50, 5-56, 5-58, 7-3
CSOR D-18
CSORBT D-18
CSPAR D-15
CTD9 D-62
CTM Reference Manual 10-1
CTM2C D-62
CTM4
CWP D-36
Cyclic redundancy check error (CRCERR) D-94
DAC 8-1
DASM 10-10
DASMA D-66
DASMB D-67
DASMSIC D-63
DATA 5-21
Data
DATA (definition) 2-8
DBcc 4-15
DC characteristics (electricals) A-4
MOTOROLA
I-4
reset values 5-63
address map 10-2, D-56
block diagram 10-1
bus interface unit submodule (BIUSM) 10-3
components 10-1
counter prescaler submodule (CPSM) 10-4
double-action submodule (DASM) 10-10
features 3-2
free-running counter submodule (FCSM) 10-5
interrupt priority and vector/pin allocation 10-18
interrupts 10-18
modulus counter submodule (MCSM) 10-5, 10-7
pulse width modulation submodule (PWMSM) 10-12
block diagram 10-11
channels 10-10
interrupts 10-12
mode flag status bit states D-64
modes of operation 10-10
registers 10-12
timing (electricals) A-33
operations D-67
operations D-68
and size acknowledge (DSACK) 5-14, 5-23
bus
field for RX/TX frames (TouCAN) 13-4
frame 9-25
multiplexer 5-25
strobe (DS) 5-22
types 4-4
data register A (DASMA) D-66
data register B (DASMB) D-67
status/interrupt/control
mode selection 5-42
signals (DATA) 5-21
D-63
–D–
register
(DASMSIC)
DCNR D-80
DDRE 5-64, D-10
DDRF 5-64, D-11
DDRQA 8-2, D-30
DDRQS 9-4, 9-16, 9-19, D-47
Delay
Designated CPU space 5-22
Development
DFC 4-7
Digital
DIO 11-6
DIS D-67, D-68
Disabled mode 8-20
Discrete input/output (DIO) 11-6
Distributed register (DREG) D-21
DIV8 clock 11-15
Divide by 2/divide by 3 (DIV23) D-59
Double
DREG D-21
Drive time base bus (DRV) D-60, D-61
DRV D-60, D-61
DS 5-22, 5-27, 5-37
DSACK 5-14, 5-27, 5-31, 5-53, 5-58, 5-60
DSCK D-55
DSCKL D-50
DSCLK 4-24
DSCR D-75
DSSR D-76
DT D-54
DTL D-51
Dynamic bus sizing 5-24
EBI 5-52
ECLK 5-12
Edge polarity (EDPOL) bit D-65
after transfer (DT) 9-18, D-54
before SCK (DSCKL) D-50
support and test registers (TPU) 11-17
tools and support C-1
control section
input
to analog converter (DAC) 8-1, 8-15
-action submodule. See DASM 10-10
-buffered 9-26, 9-28
bus fault 4-20, 5-36
-row header 4-25
assertion results 5-35
external/internal generation 5-30
option fields 5-30
signal effects 5-24
source specification in asynchronous mode 5-60,
bus timing A-21
output timing diagram A-10
timing diagram A-22
contents 8-1, 8-16–??
/output port (PQA) 8-4
port (PQB) 8-4
D-19
–E–
USER’S MANUAL
MC68336/376