RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 249

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
10.3.2 Single Read Cycle, Wait States Inserted By Memory Arbitration
Figure 10-3. Local Processor Single Read Cycle with Arbitration Wait States
28234-DSH-001-B
LADDR[18:2]
LDATA[31:0]
PADDR[1:0]
LADDR[1:0]
PBSEL[1:0]
MWE*[3:0]
MCS*[3:0]
PBLAST*
SYSCLK
PBE[3:0]
PDAEN*
PWAIT*
D[31:0]
PRDY*
A[20:4]
PWNR
DT/R*
MOE*
PCS*
PAS*
1.
Address
Cycle
ta
11
10
Figure 10-3
states. This example is similar to the preceding one, except that here the local
processor is not able to access the RAM immediately because of higher priority
memory requests on cycles two and three. On cycle four, the memory controller
allows the local processor access to the address and data bus and the transaction
takes place at the end of cycle six.
1
2.
Arbitration
Cycle
tarb
Mindspeed Technologies
illustrates a local processor single read cycle with arbitration wait
2
3.
Arbitration
Cycle
tarb
A0
3
4.
Arbitration
Cycle
tarb
4
5.
™
Bus
Recovery
Cycle
tbr
A0
5
6. Data
10.0 Local Processor Interface
Cycle
td
0111
10
10.3 Bus Cycle Descriptions
D0
D0
6
7.
Arbitration
Cycle
tarb
7
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10-7