RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 264

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

11.0 PCI Bus Interface
11.4 PCI Bus Master Logic
11-4
11.4 PCI Bus Master Logic
The PCI bus master logic block is responsible for accepting read and write
commands from the DMA coprocessor (passed via the burst FIFO buffers), and in
turn acquiring mastership of the PCI bus and generating transactions to perform
the actual data transfers. The bus master logic contains the following:
read or a write transfer, using the defined PCI protocol sequence. In this case, the
bus master logic will terminate the current burst, maintain its bus request, and
restart the transfer at the point of termination. Disconnects and retries are not
regarded as errors.
transaction. If any of the following five errors occur, the bus master logic will
permanently terminate the transaction, flag an error, and cease to process any
more commands.
• A command decoder that interprets commands issued from the DMA
• A burst controller that counts off read and write cycles in each burst on the
• Arbitration logic that acquires control of the PCI bus.
• Arbitration parking.
• A bus state machine that sequences and controls transfers.
It is possible for the addressed slave to request a disconnect or a retry during a
Five possible sources of error are present during any PCI bus master
1.
2.
3.
coprocessor.
PCI bus (and also latches and drives the address and command during the
address phase of each transfer).
Target Abort—The PCI transaction will terminate if the addressed target
signals a target abort. In this case, the RTA and MERROR bits in the PCI
Configuration Register space will be set and the PCI_BUS_STATUS[4] bit
in the SYS_STAT Register will be set.
Master Abort—If the addressed target does not respond with an
HDEVSEL* assertion, then a master abort is flagged. In this case, the
RMA and MERROR bits in the PCI Configuration Register space will be
set and the PCI_BUS_STATUS[3] bit in the SYS_STAT Register will be
set.
Parity Error—If the data parity checked during read transfers is
inconsistent with the state of the HPAR signal, then a parity error is
signaled. In this case, the DPR and MERROR bits in the PCI
Configuration Register space will be set and the PCI_BUS_STATUS[2] bit
in the SYS_STAT Register will be set.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234