RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 299

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
13.5 Reassembly Registers
0xf0 - Reassembly Control Register 0 (RSM_CTRL0)
The Reassembly Control Register 0 contains the general control bits for the reassembly coprocessor. The
assertion of the HRST* system reset pin or the GLOBAL_RESET bit in the CONFIG0 register will clear the
RSM_ENABLE control bit.
28234-DSH-001-B
27-24
23-18
Bit
31
30
29
28
17
16
15
14
13
Field
Size
1
1
1
1
4
6
1
1
1
1
1
RSM_ENABLE
RSM_RESET
Reserved
VPI_MASK
Reserved
Reserved
RSM_PHALT
Reserved
FWALL_EN
RSM_FBQ_DIS
RSM_STAT_DIS
Name
Mindspeed Technologies
Reassembly enable. Initiates an incoming transfer if set, and halts it if reset.
If this bit is reset while the reassembly coprocessor is running, it
temporarily suspends the activities of the reassembly coprocessor logic.
Suspension takes place on a cell boundary, i.e., between the completion of
all processing and transfers required for the current cell, and the start of
processing for the next cell. The hold can be removed and the transfer
resumed by setting the RSM_ENABLE bit. This bit will also be set low
internally on certain reassembly error conditions. This includes parity error
with PHALT_EN. In this case, the error condition should be corrected and
the RSM_ENABLE bit set high to resume operation.
Reassembly reset. Forces a hardware reset of the reassembly coprocessor
when asserted. It must be deasserted before the reassembly coprocessor
will resume normal operation.
Program and read as zero.
VPI Mask enable. Used to select UNI/NNI header operation in the direct
index method. When a logic high, the four MSBs of the header are masked
for UNI operation. This also controls the Index Table size. A UNI table is 256
entries and a NNI table is 4,096.
Program and read as zero.
Program and read as zero.
Reassembly coprocessor halt on parity error detect. The reassembly
coprocessor will halt the incoming channel logic if a parity error is detected
and the RSM_PHALT bit is set.
Program and read as zero.
Firewall enable. Enables free buffer queue firewalling of user cells. If set,
this bit enables the per connection free buffer queue firewall. Each
connection that firewall is active in must have the FW_EN bit set to a logic
high in the VCC table.
Free Buffer Queue Underflow Protection Disable. When a logic high, the
reassembly coprocessor ignores the VLD bit in the free buffer queue when a
new buffer is required. The periodic writing of the read index pointer to
host/SAR shared memory is also disabled.
Status Queue Overflow Protection Disable. When a logic high, the
reassembly coprocessor ignores the READ_UD pointer.
™
Description
13.5 Reassembly Registers
13.0 RS8234 Registers
13-17