RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 66

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (6 of 6)
2-34
TRST*
TCLK
TMS
TDO
TDI
SDA
SCL
VDD
VSS
VGG
Pin Label
Test Logic Reset
Test Clock
Test Mode Select
Serial Test Data
Serial Test Data
EEPROM Data
EEPROM Clock
Power
Ground
ESD Protection –
Voltage Clamp
Signal Name
Mindspeed Technologies
I/O
I/O
—
—
O
O
I
I
I
I
I
When a logic low, this signal asynchronously resets the
boundary scan test circuitry and puts the test controller into
the reset state. This state allows normal system operation. Tie
to ground when boundary scan is not implemented. This pad
has an internal pullup resister to VDD.
Generated externally by the system board or by the tester. Tie
to ground when boundary scan is not implemented.
Decoded to control test operations. This pad has an internal
pullup resister to VDD.
Outputs serial test pattern data.
Input for serial test pattern data. This pad has an internal
pullup resister to VDD.
Serial I
Serial I
49 balls are provided for supply voltage.
85 balls are provided for ground. (The 36 balls in the center
help in heat dissipation.)
Provides Electrostatic Discharge (ESD) protection and over
voltage protection. When the device is used with 5 V devices
on the board, tie this pin to 5 V for 5 V signal tolerance.
Otherwise, tie to 3.3 V.
NOTE:
V supply.
ATM ServiceSAR Plus with xBR Traffic Management
2
2
C data.
C clock.
The 5 V supply must be applied concurrent to the 3.3
™
Definition
28234-DSH-001-B
RS8234