STA333W13TR STMicroelectronics, STA333W13TR Datasheet - Page 18

• Manufacturer Part Number: STA333W13TR
• Description: IC DAS 2CH MICROLESS POWERSSO36
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Audio Processorr

Specifications of STA333W13TR

• Applications: DVD
• Mounting Type: Surface Mount
• Package / Case: 36-BFSOP (0.295", 7.50mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11457-2

I
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
18/49
2
C bus specification
I
The STA333W supports the I
defines any device that sends data on to the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the data transfer is known as the master and
the other as the slave. The master always starts the transfer and provides the serial clock for
synchronization. The STA333W is always a slave device in all of its communications. It
supports up to 400 kb/s (fast-mode bit rate).
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA333W and the bus master.
Data input
During the data input the STA333W samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA333W, the master must initiate a
start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)
corresponding to the device-select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA333W the I
port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and
0 for write mode. After a START condition the STA333W identifies the device address on the
SDA bus and if a match is found, acknowledges the identification during the 9th bit time. The
byte following the device identification byte is the internal space address.
2
C bus specification
2
C protocol via the input ports SCL and SDA. This protocol
Doc ID 13365 Rev 2
2
C interface has two device addresses depending on the SA
STA333W
2
C bus