STA333W13TR STMicroelectronics, STA333W13TR Datasheet - Page 39

• Manufacturer Part Number: STA333W13TR
• Description: IC DAS 2CH MICROLESS POWERSSO36
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Audio Processorr

Specifications of STA333W13TR

• Applications: DVD
• Mounting Type: Surface Mount
• Package / Case: 36-BFSOP (0.295", 7.50mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11457-2

STA333W
7
7.1
7.2
Applications information
Applications scheme for power supplies
Figure 11
Special care has to be taken with regard to the power supplies when laying out the PCB. In
particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close
as possible to the device. This prevents unwanted oscillation on the digital parts of the
device due to the inductive effects of the PCB tracks. The same rule also applies to all the
decoulpling capacitors; they should be placed as close as possible to the device in order to
limit the effect of spikes on the supplies.
Figure 11. Applications diagram
PLL filter
It is recommended to use the circuit in
best performance from the device in general applications. Note that the ground of this filter
has to be connected to the ground of the PLL without any resistive path.
For the component values, it should be remembered that the greater the filter bandwidth, the
shorter the lock time but the higher the PLL output jitter.
1000uF 35V
1000uF 35V
1000uF 35V
1uF 35V
1uF 35V
1uF 35V
100nF
100nF
100nF
1uF 35V
1uF 35V
1uF 35V
100nF
100nF
100nF
below shows a typical applications scheme for STA333W.
VCC
VCC
VCC
OUT2B
OUT2B
OUT2B
OUT2B
OUT2B
OUT2B
OUT2A
OUT2A
OUT2A
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
OUT1A
OUT1A
OUT1A
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
Doc ID 13365 Rev 2
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
17
17
17
18
18
18
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
GND_SUB
GND_SUB
GND_SUB
SA
SA
SA
TEST_MODE
TEST_MODE
TEST_MODE
VSS
VSS
VSS
VCC_REG
VCC_REG
VCC_REG
OUT2B
OUT2B
OUT2B
GND2
GND2
GND2
VCC2
VCC2
VCC2
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
VCC1
VCC1
VCC1
GND1
GND1
GND1
OUT1A
OUT1A
OUT1A
GND_REG
GND_REG
GND_REG
VDD
VDD
VDD
CONFIG
CONFIG
CONFIG
NC
NC
NC
NC
NC
NC
Figure 12
FILTER_PLL 25
FILTER_PLL 25
FILTER_PLL 25
GND_DIG 35
GND_DIG 35
GND_DIG 35
PLL_GND 26
PLL_GND 26
PLL_GND 26
GND_DIG 22
GND_DIG 22
GND_DIG 22
VDD_DIG 36
VDD_DIG 36
VDD_DIG 36
VDD_PLL 24
VDD_PLL 24
VDD_PLL 24
VDD_DIG 21
VDD_DIG 21
VDD_DIG 21
INT_LINE 32
INT_LINE 32
INT_LINE 32
PWRDN
PWRDN
PWRDN
RESET 31
RESET 31
RESET 31
LRCKI
LRCKI
LRCKI
BICKI
BICKI
BICKI
SDA
SDA
SDA
SCL
SCL
SCL
SDI
SDI
SDI
XTI 27
XTI 27
XTI 27
below for the PLL loop filter to achieve the
NC 20
NC 20
NC 20
NC 19
NC 19
NC 19
34
34
34
33
33
33
30
30
30
29
29
29
28
28
28
23
23
23
3R3
3R3
3R3
PLL_FILT
PLL_FILT
PLL_FILT
PLL_FILT
PLL_FILT
PLL_FILT
3R3
3R3
3R3
SCL
SCL
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SDA
SDA
INTL
INTL
INTL
DATA
DATA
DATA
DATA
DATA
DATA
LRCKI
LRCKI
LRCKI
LRCKI
LRCKI
LRCKI
BICKI
BICKI
BICKI
BICKI
BICKI
BICKI
XTI
XTI
XTI
XTI
XTI
XTI
100nF
100nF
100nF
100nF
100nF
100nF
Applications information
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
GND_DIG
GND_DIG
GND_DIG
100nF
100nF
100nF
100nF
100nF
100nF
BEAD
BEAD
BEAD
BEAD
BEAD
BEAD
3V3
3V3
3V3
10K
10K
10K
1nF
1nF
1nF
1nF
1nF
1nF
GND_DIG
GND_DIG
GND_DIG
PLL_GND
PLL_GND
PLL_GND
GND_DIG
GND_DIG
GND_DIG
BEAD
BEAD
BEAD
RESET
RESET
RESET
RESET
RESET
RESET
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
RESET
RESET
RESET
RESET
RESET
RESET
GND_DIG
GND_DIG
GND_DIG
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