AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 14

• Manufacturer Part Number: AM186CC-40KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-40KI\W C

• Lead Free Status / Rohs Status: Not Compliant

14
Signal Name
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0
AD15–AD0
ALE
ARDY
Multiplexed
Signal(s)
—
—
[PIO33]
[PIO8]
Am186™CC Communications Controller Data Sheet
Type Description
STI
O
B
O
Table 4. Signal Descriptions
Address Bus supplies nonmultiplexed memory or I/O addresses to the system
one half of a CLKOUT period earlier than the multiplexed address and data bus
(AD15–AD0). During bus-hold or reset conditions, the address bus is three-
stated with pulldowns.
When the lower or upper chip-select regions are configured for DRAM mode, the
A19–A0 bus provides the row and column addresses at the appropriate times.
The upper and lower memory chip-select ranges can be individually configured
for DRAM mode.
Address and Data Bus time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an address to the system during the
first period of a bus cycle (t
data to or from the system during the remaining periods of that cycle (t2, t3, and
t4). The address phase of these pins can be disabled—see the {ADEN} pin
description in Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.
During a reset condition, the address and data bus is three-stated with
pulldowns, and during a bus hold it is three-stated.
In addition, during a reset the state of the address and data bus pins (AD15–
AD0) is latched into the Reset Configuration (RESCON) register. This feature
can be used to provide software with information about the external system at
reset time.
Address Latch Enable indicates to the system that an address appears on the
address and data bus (AD15–AD0). The address is guaranteed valid on the
falling edge of ALE.
ALE is three-stated and has a pulldown resistor during bus-hold or reset
conditions.
Asynchronous Ready is a true asynchronous ready that indicates to the
Am186CC controller that the addressed memory space or I/O device will
complete a data transfer. The ARDY pin is asynchronous to CLKOUT and is
active High. To guarantee the number of wait states inserted, ARDY or SRDY
must be synchronized to CLKOUT. If the falling edge of ARDY is not
synchronized to CLKOUT as specified, an additional clock period can be added.
To always assert the ready condition to the microcontroller, tie ARDY and SRDY
High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
1
). It transmits (write cycle) or receives (read cycle)