AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 21

• Manufacturer Part Number: AM186CC-40KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-40KI\W C

• Lead Free Status / Rohs Status: Not Compliant

Signal Name
INTERRUPTS
NMI
[INT8]
[INT7]
[INT6]
INT5–INT0
Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35. (See the
Am186™CC/CH/CU Microcontrollers User’s Manual , order #21914 for more information.)
Multiplexed
Signal(s)
—
[PWD]
PIO6
PIO7
PIO19
—
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
STI
STI
STI
STI
STI
Nonmaskable Interrupt indicates to the Am186CC controller that an interrupt
request has occurred. The NMI signal is the highest priority hardware interrupt and
cannot be masked. The controller always transfers program execution to the
location specified by the nonmaskable interrupt vector in the controller’s interrupt
vector table when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not participate in the
priority resolution process of the maskable interrupts. There is no bit associated
with NMI in the interrupt in-service or interrupt request registers. This means that
a new NMI request can interrupt an executing NMI interrupt service routine. As
with all hardware interrupts, the interrupt flag (IF) is cleared when the processor
takes the interrupt, disabling the maskable interrupt sources. However, if
maskable interrupts are re-enabled by software in the NMI interrupt service
routine (for example, via the STI instruction), the fact that an NMI is currently in
service does not have any effect on the priority resolution of maskable interrupt
requests. For this reason, it is strongly advised that the interrupt service routine
for NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized internally, and it
initiates the interrupt at the next instruction boundary. To guarantee that the interrupt
is recognized, the NMI pin must be asserted for at least one CLKOUT period.
The board designer is responsible for properly terminating the NMI input.
Maskable Interrupt Requests 8–0 indicate to the Am186CC controller that an
external interrupt request has occurred. If the individual pin is not masked, the
controller transfers program execution to the location specified by the associated
interrupt vector in the controller’s interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. The interrupt polarity is programmable. To guarantee interrupt
recognition for edge-triggered interrupts, the user should hold the interrupt
source for a minimum of five system clocks. A second interrupt from the same
source is not recognized until after an acknowledge of the first.
The board designer is responsible for properly terminating the INT8–INT0 inputs.
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