AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 20

• Manufacturer Part Number: AM186CC-40KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-40KI\W C

• Lead Free Status / Rohs Status: Not Compliant

20
Signal Name
[PCS7]
[PCS6]
[PCS5]
[PCS4]
PCS3
PCS2
PCS1
PCS0
UCS
DRAM
[CAS1]
[CAS0]
[RAS1]
[RAS0]
Multiplexed
Signal(s)
PIO31
PIO32
PIO2
PIO3
{CLKSEL2}
—
—
[PIO14]
{USBSEL2}
[PIO13]
{USBSEL1}
{ONCE}
MCS1
MCS2
[MCS3]
PIO5
LCS
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
O
O
O
O
O
Peripheral Chip Selects 7–0 indicate to the system that an access is in
progress to the corresponding region of the peripheral address block (either I/O
or memory address space). The base address of the peripheral address block is
programmable. PCS7–PCS0 are three-stated with pullup resistors during bus-
hold or reset conditions.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed
AD address and data bus timing.
Upper Memory Chip Select indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the upper
memory block are programmable up to 512 Kbytes. UCS is three-stated with a
weak pullup during bus-hold or reset conditions.
The UCS can be configured for an 8-bit or 16-bit bus size out of reset. For
additional information, see the {UCSX8} pin description in Table 31, “Reset
Configuration Pins (Pinstraps),” on page A-10.
After reset, UCS is active for the 64-Kbyte memory range from F0000h to FFFFFh,
including the reset address of FFFF0h.
Column Address Strobes 1–0: When either the upper or lower chip select
regions are configured for DRAM, these pins provide the column address strobe
signals to the DRAM. The CAS signals can be used to perform byte writes in a
manner similar to WHB and WLB, respectively (i.e., [CAS0] corresponds to the
low byte (WLB) and [CAS1] corresponds to the high byte (WHB)).
Row Address Strobe 1: When the upper chip select region is configured to
DRAM, this pin provides the row address strobe signal to the upper DRAM bank.
Row Address Strobe 0: When the lower chip select region is configured to
DRAM, this pin provides the row address strobe signal to the lower DRAM bank.