AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 59

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AM186CC-40KI\W C

Manufacturer Part Number
AM186CC-40KI\W C
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AM186CC-40KI\W C

Lead Free Status / Rohs Status
Not Compliant
Notes:
1. All timing parameters are measured at V
2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly.
3. Testing is performed with equal loading on referenced pins.
4. The timing of this signal is the same for a read cycle, whether it is configured to be DEN or DS.
Read Cycle Timing Responses
No.
21
22
23
24
25
26
27
28
29
59
66
67
68
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
Symbol Description
t
t
t
CEVDX
CHCTV
t
t
t
t
t
CHCSV
t
t
t
t
t
RLRH
CLRH
RHLH
RHAV
RHDX
CHAV
LHAV
AZRL
CLRL
AVRL
Parameter
DEN/DS inactive
delay
Control active
delay 2
ALE High to
address valid
AD address float to
RD active
RD active delay
RD pulse width
RD inactive delay
RD inactive to ALE
High
RD inactive to AD
address active
RD High to data
hold on AD Bus
A address valid to
RD Low
CLKOUT High to
LCS/UCS valid
CLKOUT High to A
address valid
3
4
Am186™CC Communications Controller Data Sheet
3
2
Table 11. Read Cycle Timing
1.5t
2t
t
CC
CLCL
CLCL
CLCL
t
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
CLCH
Min
15
–10=30
0
0
0
0
–15=65
0
3
0
0
25 MHz
–15=45
–3
Max
20
20
20
20
20
20
2t
1.5t
t
CLCL
CLCL
t
CLCH
CLCL
1
27.5
Preliminary
Min
7.5
(Continued)
0
0
0
0
–10=40
0
–5=20
2
0
0
40 MHz
–2
–10=
Max
12
12
10
12
10
10
1.5t
2t
(Commercial Only)
t
CLCL
CLCL
CLCL
t
CLCH
Min
0
0
5
0
0
0
0
0
0
–10=30
–5=15
50 MHz
–10=20
–2
Max
10
10
10
10
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
59

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