AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 15

• Manufacturer Part Number: AM186CC-40KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-40KI\W C

• Lead Free Status / Rohs Status: Not Compliant

Signal Name
BHE
BSIZE8
DEN
[DS]
DT/R
DRQ1
[DRQ0]
Multiplexed
Signal(s)
[PIO34]
{ADEN}
—
[DS]
[PIO30]
DEN
PIO30
[PIO29]
—
PIO9
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
STI
STI
O
O
O
O
O
Bus High Enable: During a memory access, BHE and the least-significant
address bit (AD0) indicate to the system which bytes of the data bus (upper,
lower, or both) participate in a bus cycle. The BHE and AD0 pins are encoded as
follows:
BHE is asserted during t
require latching. BHE is three-stated with a pullup during bus-hold and reset
conditions.
WLB and WHB implement the functionality of BHE and AD0 for high and low byte
write enables, and they have timing appropriate for use with the nonmultiplexed
bus interface.
BHE also signals DRAM refresh cycles when using the multiplexed address and
data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High.
During refresh cycles, the AD bus is driven during the t
during the t
a refresh cycle. For this reason, the A0 signal cannot be used in place of the AD0
signal to determine refresh cycles.
Bus Size 8 is asserted during t
indicate a 16-bit cycle.
Data Enable supplies an output enable to an external data-bus transceiver. DEN
is asserted during memory and I/O cycles. DEN is deasserted when DT/R
changes state. DEN is three-stated with a pullup during bus-hold or reset
conditions.
Data Strobe provides a signal where the write cycle timing is identical to the read
cycle timing. When used with other control signals, [DS] provides an interface for
68K-type peripherals without the need for additional system interface logic.
When [DS] is asserted, addresses are valid. When [DS] is asserted on writes,
data is valid. When [DS] is asserted on reads, data can be driven on the AD bus.
Following a reset, this pin is configured as DEN. The pin is then configured by
software to operate as [DS].
Data Transmit or Receive indicates which direction data should flow through an
external data-bus transceiver. When DT/R is asserted High, the Am186CC
controller transmits data. When this pin is deasserted Low, the controller
receives data. DT/R is three-stated with a pullup during a bus-hold or reset
condition.
DMA Requests 1 and 0 indicate to the Am186CC controller that an external
device is ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are
level-triggered and internally synchronized. DRQ1–[DRQ0] are not latched and
must remain active until serviced.
BHE
0
0
1
1
2
, t
3
, and t
4
phases. The value driven on the A bus is undefined during
1
AD0
and remains asserted through t
0
1
0
1
Data Byte Encoding
1
–t
4
to indicate an 8-bit cycle, or is deasserted to
Type of Bus Cycle
Word transfer
High byte transfer (bits 15–8)
Low byte transfer (bits 7–0)
Refresh
1
phase and three-stated
3
and t
W
. BHE does not
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