AM186CC-40KI\W C AMD (ADVANCED MICRO DEVICES), AM186CC-40KI\W C Datasheet - Page 52

• Manufacturer Part Number: AM186CC-40KI\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-40KI\W C

• Lead Free Status / Rohs Status: Not Compliant

52
USB Timing (Clocks)
USB Timing (Data/Jitter)
DCE
PCM (Slave)
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
t
Symbol
t
TCLKPER
t
t
t
t
t
t
t
t
TCLKHD
t
t
TCLKSU
WHDEX
t
t
t
t
t
UCHCK
t
UCKHL
UCKLH
UCLCK
t
t
SYNSS
TCLKH
TCLKO
TCLKR
t
t
WHDX
WLWH
UCKIN
TCLKL
WHLH
t
t
t
WSYN
t
t
SUDC
SUFC
CLKP
DCLT
t
t
t
t
t
t
t
DCD
DTW
HCD
t
t
DCT
HCF
DFT
DZF
DZF
DTZ
JR1
JR2
WH
HFI
WL
t
t
R
F
Am186™CC Communications Controller Data Sheet
No.
35
34
33
32
13
11
12
17
10
14
15
16
18
3
4
1
5
2
2
3
4
1
2
6
3
4
1
7
5
1
8
5
6
4
9
7
2
3
Description
Data hold after WR
Delay from CLK Low of last bit to TSC invalid
Delay to TSC valid from CLK
Delay to TSC valid from FSC
Hold time from CLK Low to RXD invalid
Hold time from CLK Low to FSC invalid
WR inactive to DEN inactive
WR inactive to ALE High
WR pulse width
USBX1 High time
USBX1 fall time
USBX1 period
USBX1 rise time
USBX1 Low time
Fall time
Consecutive transition jitter
Paired transition jitter
Rise time
DCE clock High
DCE clock hold
DCE clock Low
DCE clock to output delay
DCE clock period
DCE clock rise/fall
DCE clock setup
PCM clock period
Delay time from CLK High to TXD valid
Delay from last bit CLK Low to TXD weak drive
Delay time to valid TXD from CLK
Delay time to valid TXD from FSC
Hold time from CLK Low to FSC valid
Setup time from RXD valid to CLK
Setup time for FSC High to CLK Low
Time between successive synchronization pulses
PCM clock High
PCM clock Low
FSC width invalid
Delay from last bit CLK (plus one) High to TXD disable