LPC2420FBD208-S

Manufacturer Part NumberLPC2420FBD208-S
DescriptionMCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
ManufacturerNXP Semiconductors
LPC2420FBD208-S datasheet
 


Specifications of LPC2420FBD208-S

Package208LQFPDevice CoreARM7TDMI-S
Family NameLPC2000Maximum Speed72 MHz
Ram Size82 KBOperating Supply Voltage3.3 V
Data Bus Width16|32 BitProgram Memory TypeROMLess
Number Of Programmable I/os160Interface TypeI2C/I2S/SPI/SSP/UART/USB
On-chip Adc8-chx10-bitOn-chip Dac1-chx10-bit
Operating Temperature-40 to 85 °CNumber Of Timers4
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LPC2420/2460
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 05 — 24 February 2010
1. General description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means
engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2420/2460 microcontroller is ideal for multi-purpose communication applications.
It incorporates a 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), a USB
full-speed device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two
Controller Area Network (CAN) channels (LPC2460 only), an SPI interface, two
Synchronous Serial Ports (SSP), three I
this collection of serial communications interfaces are the following feature components;
an on-chip 4 MHz internal precision oscillator, 82/98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet (LPC2460 only), 16 kB SRAM for general
purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller
(EMC). These features make this device optimally suited for communication gateways
and protocol converters. Complementing the many serial communication controllers,
versatile clocking capabilities, and memory features are various 32-bit timers, an
improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to
160 fast GPIO lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware
based Vector Interrupt Controller (VIC) that means these external inputs can generate
edge-triggered interrupts. All of these features make the LPC2420/2460 particularly
suitable for industrial control and medical systems.
2. Features
ARM7TDMI-S processor, running at up to 72 MHz.
82/98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
(LPC2460 only)
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
Preliminary data sheet
2
2
C interfaces, and an I
S interface. Supporting

LPC2420FBD208-S Summary of contents

  • Page 1

    ... ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 05 — 24 February 2010 1. General description NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both 32-bit ARM and 16-bit Thumb instructions ...

  • Page 2

    ... NXP Semiconductors Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, and USB DMA with no contention (LPC2460 only). EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM. Advanced Vectored Interrupt Controller (VIC), supporting vectored interrupts. ...

  • Page 3

    ... Ordering information Type number Package Name LPC2420FBD208 LQFP208 LPC2420FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm SOT950-1 LPC2460FBD208 LQFP208 LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm SOT950-1 ...

  • Page 4

    ... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) LPC2420FBD208 N LPC2420FET208 N LPC2460FBD208 N LPC2460FET208 N LPC2420_60_5 Preliminary data sheet SRAM (kB) External Ethernet bus Full 32-bit - 98 Full 32-bit MII/RMII 98 Full 32-bit MII/RMII 98 Full 32-bit MII/RMII Rev. 05 — 24 February 2010 LPC2420/2460 Flashless 16-bit/32-bit microcontroller ...

  • Page 5

    ... NXP Semiconductors 5. Block diagram LPC2420/2460 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 ETHERNET MII/RMII MAC WITH (1) DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × MAT1 6 × PWM0/PWM1 PWM0, PWM1 1 × PCAP0, 2 × PCAP1 ...

  • Page 6

    ... Fig 2. LPC2420/2460 pinning LQFP208 package Fig 3. LPC2420/2460 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 LPC2420_60_5 Preliminary data sheet 1 LPC2420FBD208 LPC2460FBD208 52 ball A1 index area ...

  • Page 7

    ... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 17 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] Row B 1 P3[2]/ P1[1]/ENET_TXD1 6 9 P4[25]/ DD(3V3) 17 P2[0]/PWM1[1]/TXD1/ TRACECLK Row C 1 P3[13]/D13 2 5 P3[9]/ DD(3V3) 13 P0[7]/I2STX_CLK/SCK1 14 /MAT2[ DD(3V3) Row D 1 TRST 2 5 P3[11]/D11 ...

  • Page 8

    ... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row H 1 P0[23]/AD0[0]/ 2 I2SRX_CLK/CAP3[ SSIO Row J 1 P3[6]/ P0[16]/RXD1/ 15 SSEL0/SSEL Row K 1 VREF 2 14 P4[22]/A22/ 15 TXD2/MISO1 Row L 1 P3[7]/ n.c. 15 Row M 1 P3[15]/D15 2 14 P4[6]/A6 15 Row N ...

  • Page 9

    ... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 13 P2[17]/RAS 14 17 P4[20]/A20/ SDA2/SCK1 Row T 1 P0[27]/SDA0 SSIO 9 P1[24]/USB_RX_DM1/ 10 PWM1[5]/MOSI0 13 P1[28]/USB_SCL1/ 14 PCAP1[0]/MAT0[0] 17 P2[11]/EINT1/ MCIDAT1/I2STX_CLK Row U 1 USB_D− P2[23]/DYCS3/ 6 CAP3[1]/SSEL0 9 P4[0]/A0 ...

  • Page 10

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[3]/RXD0 204 D6 [1] P0[4]/ 168 B12 I2SRX_CLK/ RD2/CAP2[0] [1] P0[5]/ 166 C12 I2SRX_WS/ TD2/CAP2[1] [1] P0[6]/ 164 D13 I2SRX_SDA/ SSEL1/MAT2[0] [1] P0[7]/ 162 C13 I2STX_CLK/ SCK1/MAT2[1] [1] P0[8]/ 160 A15 I2STX_WS/ MISO1/MAT2[2] [1] P0[9]/ 158 C14 ...

  • Page 11

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [2] P0[12 USB_PPWR2/ MISO1/AD0[6] [2] P0[13 USB_UP_LED2/ MOSI1/AD0[7] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] P0[15]/TXD1/ 128 J16 SCK0/SCK [1] P0[16]/RXD1/ 130 J14 SSEL0/SSEL [1] P0[17]/CTS1/ 126 K17 MISO0/MISO [1] P0[18]/DCD1/ 124 K15 MOSI0/MOSI [1] P0[19]/DSR1/ ...

  • Page 12

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[21]/RI1/ 118 M16 MCIPWR/RD1 [1] P0[22]/RTS1/ 116 N17 MCIDAT0/TD1 [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2 I2SRX_SDA/ TXD3 [2][3] P0[26]/AD0[3 AOUT/RXD3 [4] P0[27]/SDA0 50 T1 [4] P0[28]/SCL0 48 R3 ...

  • Page 13

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[0]/ 196 A3 ENET_TXD0 [1] P1[1]/ 194 B5 ENET_TXD1 [1] P1[2]/ 185 D9 ENET_TXD2/ MCICLK/ PWM0[1] [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ PWM0[2] [1] P1[4]/ 192 A5 ENET_TX_EN [1] P1[5]/ 156 A17 ENET_TX_ER/ MCIPWR/ PWM0[3] [1] P1[6]/ 171 B11 ENET_TX_CLK/ MCIDAT0/ PWM0[4] ...

  • Page 14

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[12]/ 157 A16 ENET_RXD3/ MCIDAT3/ PCAP0[0] [1] P1[13]/ 147 D16 ENET_RX_DV [1] P1[14]/ 184 A7 ENET_RX_ER [1] P1[15]/ 182 A8 ENET_REF_CLK/ ENET_RX_CLK [1] P1[16]/ 180 D10 ENET_MDC [1] P1[17]/ 178 A9 ENET_MDIO [1] P1[18 USB_UP_LED1/ PWM1[1]/ CAP1[0] [1] P1[19 USB_TX_E1/ USB_PPWR1/ CAP1[1] ...

  • Page 15

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[23 USB_RX_DP1/ PWM1[4]/MISO0 [1] P1[24 USB_RX_DM1/ PWM1[5]/MOSI0 [1] P1[25]/ 80 T10 USB_LS1/ USB_HSTEN1/ MAT1[1] [1] P1[26]/ 82 R10 USB_SSPND1/ PWM1[6]/ CAP0[0] [1] P1[27]/ 88 T12 USB_INT1/ USB_OVRCR1/ CAP0[1] [1] P1[28]/ 90 T13 USB_SCL1/ PCAP1[0]/ MAT0[0] [1] P1[29]/ 92 U14 USB_SDA1/ PCAP1[1]/ ...

  • Page 16

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[0]/PWM1[1]/ 154 B17 TXD1/ TRACECLK [1] P2[1]/PWM1[2]/ 152 E14 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3]/ 150 D15 CTS1/ PIPESTAT1 [1] P2[3]/PWM1[4]/ 144 E16 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5]/ 142 D17 DSR1/ TRACESYNC [1] P2[5]/PWM1[6]/ ...

  • Page 17

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[9]/ 132 H16 USB_CONNECT1/ RXD2/ EXTIN0 [6] P2[10]/EINT0 110 N15 [6] P2[11]/EINT1/ 108 T17 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 106 N14 MCIDAT2/ I2STX_WS [6] P2[13]/EINT3/ 102 T16 MCIDAT3/ I2STX_SDA [6] P2[14]/CS2/ 91 R12 CAP2[0]/SDA1 ...

  • Page 18

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[20]/DYCS0 73 T8 [1] P2[21]/DYCS1 81 U11 [1] P2[22]/DYCS2/ 85 U12 CAP3[0]/SCK0 [1] P2[23]/DYCS3 CAP3[1]/SSEL0 [1] P2[24 CKEOUT0 [1] P2[25 CKEOUT1 [1] P2[26 CKEOUT2/ MAT3[0]/MISO0 [1] P2[27 CKEOUT3/ MAT3[1]/MOSI0 [1] P2[28 DQMOUT0 [1] P2[29 DQMOUT1 [1] P2[30]/ ...

  • Page 19

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[1]/D1 201 B3 [1] P3[2]/D2 207 B1 [1] P3[3]/ [1] P3[4]/ [1] P3[5]/ [1] P3[6]/ [1] P3[7]/ [1] P3[8]/D8 191 D8 [1] P3[9]/D9 199 C5 [1] P3[10]/D10 205 B2 [1] P3[11]/D11 208 D5 [1] P3[12]/D12 1 D4 [1] P3[13]/D13 7 C1 [1] P3[14]/D14 ...

  • Page 20

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[17]/D17/ 143 F15 PWM0[2]/RXD1 [1] P3[18]/D18/ 151 C15 PWM0[3]/CTS1 [1] P3[19]/D19/ 161 B14 PWM0[4]/DCD1 [1] P3[20]/D20/ 167 A13 PWM0[5]/DSR1 [1] P3[21]/D21/ 175 C10 PWM0[6]/DTR1 [1] P3[22]/D22/ ...

  • Page 21

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[27]/D27/ 203 A1 CAP1[0]/ PWM1[4] [1] P3[28]/D28 CAP1[1]/ PWM1[5] [1] P3[29]/D29 MAT1[0]/ PWM1[6] [1] P3[30]/D30 MAT1[1]/ RTS1 [1] P3[31]/D31 MAT1[2] P4[0] to P4[31] [1] P4[0]/ [1] P4[1]/A1 79 U10 [1] P4[2]/A2 83 T11 [1] P4[3]/A3 97 U16 ...

  • Page 22

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[9]/A9 131 H17 [1] P4[10]/A10 135 G17 [1] P4[11]/A11 145 F14 [1] P4[12]/A12 149 C16 [1] P4[13]/A13 155 B16 [1] P4[14]/A14 159 B15 [1] P4[15]/A15 173 A11 [1] P4[16]/A16 101 U17 [1] P4[17]/A17 ...

  • Page 23

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[25]/WE 179 B9 [1] P4[26]/BLS0 119 L15 [1] P4[27]/BLS1 139 G15 [1] P4[28]/BLS2/ 170 C11 MAT2[0]/TXD3 [1] P4[29]/BLS3/ 176 B10 MAT2[1]/RXD3 [1] P4[30]/CS0 187 B7 [1] P4[31]/CS1 193 A4 [8] ALARM ...

  • Page 24

    ... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball V 33, 63, L3, T5, SSIO 77, 93, R9, 114, P12, 133, N16, 148, H14, 169, E15, 189, A12, [8] 200 B6 32, 84, K4, P10, SSCORE [8] 172 D12 [ SSA V 15, 60, G3, DD(3V3) 71, 89, P6, P8, 112, U13, 125, P17, 146, ...

  • Page 25

    ... NXP Semiconductors 7. Functional description 7.1 Architectural overview The LPC2420/2460 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. ...

  • Page 26

    ... NXP Semiconductors The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance. 7.2 On-chip SRAM The LPC2420/2460 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits ...

  • Page 27

    ... NXP Semiconductors 3.75 GB Fig 4. LPC2420/2460 memory map 7.4 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...

  • Page 28

    ... NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority ...

  • Page 29

    ... NXP Semiconductors – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • ...

  • Page 30

    ... NXP Semiconductors • One AHB master for transferring data. This interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data ...

  • Page 31

    ... NXP Semiconductors 7.9 Ethernet (LPC2460 only) The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...

  • Page 32

    ... NXP Semiconductors – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. ...

  • Page 33

    ... NXP Semiconductors 7.10.2.1 Features • OHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.10.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals ...

  • Page 34

    ... NXP Semiconductors • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.12 10-bit ADC The LPC2420/2460 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.12.1 Features • 10-bit successive approximation ADC • ...

  • Page 35

    ... NXP Semiconductors • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). ...

  • Page 36

    ... NXP Semiconductors 7.17.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. ...

  • Page 37

    ... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I transmit and receive channel, each of which can operate as either a master or a slave. 7.19.1 Features • ...

  • Page 38

    ... NXP Semiconductors – Do nothing on match. 7.21 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2420/2460. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...

  • Page 39

    ... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...

  • Page 40

    ... NXP Semiconductors The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation ...

  • Page 41

    ... NXP Semiconductors PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to 7.24.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU ...

  • Page 42

    ... NXP Semiconductors 7.24.4 Power control The LPC2420/2460 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value ...

  • Page 43

    ... NXP Semiconductors 7.24.4.4 Deep power-down mode Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. This produces the lowest possible power consumption without removing power from the entire chip. Since the Deep ...

  • Page 44

    ... NXP Semiconductors 7.25 System control 7.25.1 Reset Reset has four sources on the LPC2420/2460: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in timer” ...

  • Page 45

    ... NXP Semiconductors 7.25.4 AHB The LPC2460 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, is implemented on LPC2420 as well and includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM. ...

  • Page 46

    ... NXP Semiconductors The JTAG clock (TCK) must be slower than interface to operate. 7.26.2 Embedded trace Since the LPC2420/2460 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port ...

  • Page 47

    ... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...

  • Page 48

    ... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT ...

  • Page 49

    ... NXP Semiconductors Table 7. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V LOW-level input IL voltage V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level OHS short-circuit output current ...

  • Page 50

    ... NXP Semiconductors Table 7. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold ...

  • Page 51

    ... NXP Semiconductors 9.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2420_60_5 Preliminary data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I mode Rev. 05 — ...

  • Page 52

    ... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 9.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2420_60_5 Preliminary data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − ° 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode 300 ...

  • Page 53

    ... NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2420_60_5 Preliminary data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3) ...

  • Page 54

    ... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics of USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...

  • Page 55

    Table 10. Dynamic characteristics: Static external memory interface − ° ° pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS LOW to ...

  • Page 56

    Table 10. Dynamic characteristics: Static external memory interface − ° ° pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH ...

  • Page 57

    ... NXP Semiconductors Table 11. Dynamic characteristics: Dynamic external memory interface − ° ° pF amb Symbol Parameter Common t chip select valid delay time d(SV) t chip select hold time h(S) t row address strobe valid delay time d(RASV) t row address strobe hold time h(RAS) t column address strobe valid delay time ...

  • Page 58

    ... NXP Semiconductors 10.1 Timing Fig 11. External clock timing (with an amplitude of at least V T PERIOD differential data lines Fig 12. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 13. MISO line set-up time in SSP Master mode LPC2420_60_5 Preliminary data sheet ...

  • Page 59

    ... NXP Semiconductors CS addr data t CSLOEL OE BLS Fig 14. External memory read access CS BLS/WE addr data OE Fig 15. External memory write access LPC2420_60_5 Preliminary data sheet t CSLAV OELAV t OELOEH t BLSLAV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 05 — 24 February 2010 LPC2420/2460 Flashless 16-bit/32-bit microcontroller ...

  • Page 60

    ... NXP Semiconductors Fig 16. Signal timing LPC2420_60_5 Preliminary data sheet reference clock t d(XXX) output signal (O) input signal (I) Rev. 05 — 24 February 2010 LPC2420/2460 Flashless 16-bit/32-bit microcontroller t h(XXX su(D) h(D) 002aad636 © NXP B.V. 2010. All rights reserved ...

  • Page 61

    ... NXP Semiconductors 11. ADC electrical characteristics Table 12. ADC characteristics − 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...

  • Page 62

    ... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2420_60_5 Preliminary data sheet ...

  • Page 63

    ... NXP Semiconductors AD0[y] Fig 18. Suggested ADC interface - LPC2420/2460 AD0[y] pin LPC2420_60_5 Preliminary data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE Rev. 05 — 24 February 2010 LPC2420/2460 Flashless 16-bit/32-bit microcontroller R vsi AD0[y] V EXT 002aad586 © NXP B.V. 2010. All rights reserved ...

  • Page 64

    ... NXP Semiconductors 12. DAC electrical characteristics Table 13. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L 13. Application information 13.1 Suggested USB interface solutions LPC24XX Fig 19 ...

  • Page 65

    ... NXP Semiconductors LPC24XX Fig 20. LPC2420/2460 USB interface on a bus-powered device LPC2420_60_5 Preliminary data sheet Flashless 16-bit/32-bit microcontroller V DD(3V3 USB_UP_LED 1.5 kΩ V BUS Ω USB_D Ω USB_D− SSIO, SSCORE Rev. 05 — 24 February 2010 LPC2420/2460 USB-B connector 002aad588 © NXP B.V. 2010. All rights reserved. ...

  • Page 66

    ... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 21. LPC2420/2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2420_60_5 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...

  • Page 67

    ... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 22. LPC2420/2460 USB OTG port configuration: VP_VM mode LPC2420_60_5 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N V DD Rev. 05 — 24 February 2010 ...

  • Page 68

    ... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 23. LPC2420/2460 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2420_60_5 Preliminary data sheet Ω 33 Ω 15 kΩ 15 kΩ FLAGA ENA OUTA ...

  • Page 69

    ... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 24. LPC2420/2460 USB OTG port configuration: USB port 1 host, USB port 2 host 13.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a ...

  • Page 70

    ... NXP Semiconductors Fig 25. Slave mode operation of the on-chip oscillator 13.3 XTAL and RTC Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C case of third overtone crystal usage, have a common ground plane ...

  • Page 71

    ... NXP Semiconductors Fig 27. Booting from a single 16-bit memory chip LPC2420_60_5 Preliminary data sheet CS1 16-bit BLS1 MEMORY LB BLS0 IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 Rev. 05 — 24 February 2010 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2010. All rights reserved ...

  • Page 72

    ... NXP Semiconductors 14. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 73

    ... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.6 0.4 OUTLINE VERSION IEC SOT950-1 Fig 29. Package outline SOT950-1 (TFBGA208) ...

  • Page 74

    ... NXP Semiconductors 15. Abbreviations Table 14. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA EOP ETM GP GPIO IrDA IAP ISP JTAG MII MIIM OHCI OTG PHY PLL POR PWM RMII SD/MMC SE0 SPI SSI SSP TTL UART USB LPC2420_60_5 Preliminary data sheet ...

  • Page 75

    ... NXP Semiconductors 16. Revision history Table 15. Revision history Document ID Release date LPC2420_60_5 20100224 • Modifications: Table • Table • Added LPC2420_60_4 20091015 • Modifications: Added LPC2420FET208. • Added Deep power-down mode information. • Table 6: Changed ESD min/max to −2500/+2500. • Table 7: Updated conditions and typical values for I • ...

  • Page 76

    ... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 77

    ... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

  • Page 78

    ... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 25 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 25 7.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 Memory map 7.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 27 7 ...

  • Page 79

    ... NXP Semiconductors 13.3 XTAL and RTC Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . 70 13.4 Suggested boot memory interface solutions Package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 75 17 Legal information 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 76 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ...