LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 31

• Manufacturer Part Number: LPC2420FBD208-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2420FBD208-S

• Package: 208LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Ram Size: 82 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 160
• Interface Type: I2C/I2S/SPI/SSP/UART/USB
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 1-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.9.1 Features
7.9 Ethernet (LPC2460 only)
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access
the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic
in the LPC2420/2460 takes place on a different AHB subsystem, effectively separating
Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip
memory via the EMC, as well as the SRAM located on another AHB. However, using
memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet
access to memory and increase the loading of its AHB.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
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Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
100 Base-FX, and 100 Base-T4.
pressure.
Redundancy Check (CRC) for transmit.
Rev. 05 — 24 February 2010
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2010. All rights reserved.
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