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ATmega168A

ATmega168A | |
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Manufacturer Part Number | ATmega168A |
Manufacturer | Atmel Corporation |
ATmega168A datasheets |
|
Specifications of ATmega168A | |||
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Flash (kbytes) | 16 Kbytes | Pin Count | 32 |
Max. Operating Frequency | 20 MHz | Cpu | 8-bit AVR |
# Of Touch Channels | 16 | Hardware Qtouch Acquisition | No |
Max I/o Pins | 23 | Ext Interrupts | 24 |
Usb Speed | No | Usb Interface | No |
Spi | 2 | Twi (i2c) | 1 |
Uart | 1 | Graphic Lcd | No |
Video Decoder | No | Camera Interface | No |
Adc Channels | 8 | Adc Resolution (bits) | 10 |
Adc Speed (ksps) | 15 | Analog Comparators | 1 |
Resistive Touch Screen | No | Temp. Sensor | Yes |
Crypto Engine | No | Sram (kbytes) | 1 |
Eeprom (bytes) | 512 | Self Program Memory | YES |
Dram Memory | No | Nand Interface | No |
Picopower | No | Temp. Range (deg C) | -40 to 85 |
I/o Supply Class | 1.8 to 5.5 | Operating Voltage (vcc) | 1.8 to 5.5 |
Fpu | No | Mpu / Mmu | no / no |
Timers | 3 | Output Compare Channels | 6 |
Input Capture Channels | 1 | Pwm Channels | 6 |
32khz Rtc | Yes | Calibrated Rc Oscillator | Yes |
PrevNext
tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to
on page
16.6.1
Input Capture Trigger Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the T1 pin
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-
form Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
16.6.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
16.6.3
Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
117.
”Accessing 16-bit Registers”
(Figure 17-1 on page
143). The edge detector is also
123
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