ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 14

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
7.5.1
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
7.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 7-4.
1st Instruction Execute
2nd Instruction Execute
3rd Instruction Execute
Figure 7-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7-5.
Register Operands Fetch
ALU Operation Execute
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
15
14
13
SP15
SP14
SP13
SP7
SP6
SP5
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
, directly generated from the selected clock source for the
CPU
shows the parallel instruction fetches and instruction executions enabled by the Har-
The Parallel Instruction Fetches and Instruction Executions
T1
clk
CPU
1st Instruction Fetch
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Single Cycle ALU Operation
T1
clk
CPU
Total Execution Time
Result Write Back
12
11
10
9
SP12
SP11
SP10
SP9
SP4
SP3
SP2
SP1
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
T2
T3
T2
T3
8
SP8
SPH
SP0
SPL
0
R/W
R/W
RAMEND
RAMEND
T4
T4
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