ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 267

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
24.9.3
ADCL and ADCH – The ADC Data Register
24.9.3.1
ADLAR = 0
Bit
(0x79)
(0x78)
Read/Write
Initial Value
24.9.3.2
ADLAR = 1
Bit
(0x79)
(0x78)
Read/Write
Initial Value
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
263.
24.9.4
ADCSRB – ADC Control and Status Register B
Bit
(0x7B)
Read/Write
Initial Value
• Bit 7, 5:3 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
15
14
13
12
ADC7
ADC6
ADC5
ADC4
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
15
14
13
12
ADC9
ADC8
ADC7
ADC6
ADC1
ADC0
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
ACME
R
R/W
R
R
0
0
0
0
11
10
9
8
ADC9
ADC8
ADC3
ADC2
ADC1
ADC0
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
11
10
9
8
ADC5
ADC4
ADC3
ADC2
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
”ADC Conversion Result” on
3
2
1
0
ADTS2
ADTS1
ADTS0
R
R/W
R/W
R/W
0
0
0
0
ADCH
ADCL
ADCH
ADCL
ADCSRB
267

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