ATmega168A

Manufacturer Part NumberATmega168A
ManufacturerAtmel Corporation
ATmega168A datasheets
 

Specifications of ATmega168A

Flash (kbytes)16 KbytesPin Count32
Max. Operating Frequency20 MHzCpu8-bit AVR
# Of Touch Channels16Hardware Qtouch AcquisitionNo
Max I/o Pins23Ext Interrupts24
Usb SpeedNoUsb InterfaceNo
Spi2Twi (i2c)1
Uart1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorYes
Crypto EngineNoSram (kbytes)1
Eeprom (bytes)512Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers3Output Compare Channels6
Input Capture Channels1Pwm Channels6
32khz RtcYesCalibrated Rc OscillatorYes
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Page 15/567

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7.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 297
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
280.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
for details.
”Interrupts” on page 59
”Boot Loader Support – Read-While-Write Self-Programming” on page
”Memory Program-
”Interrupts” on page
59. The list also
for more information.
15