ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 76

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
13.2.6
PCMSK2 – Pin Change Mask Register 2
Bit
(0x6D)
Read/Write
Initial Value
• Bit 7:0 – PCINT[23:16]: Pin Change Enable Mask 23...16
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
13.2.7
PCMSK1 – Pin Change Mask Register 1
Bit
(0x6C)
Read/Write
Initial Value
• Bit 7 – Reserved
This bit is an unused bit in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as
zero.
• Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14...8
Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[14:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[14:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
13.2.8
PCMSK0 – Pin Change Mask Register 0
Bit
(0x6B)
Read/Write
Initial Value
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7...0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
7
6
5
4
PCINT23
PCINT22
PCINT21
PCINT20
R/W
R/W
R/W
R/W
0
0
0
0
7
6
5
4
PCINT14
PCINT13
PCINT12
R
R/W
R/W
R/W
0
0
0
0
7
6
5
4
PCINT7
PCINT6
PCINT5
PCINT4
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
PCINT19
PCINT18
PCINT17
PCINT16
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
PCINT11
PCINT10
PCINT9
PCINT8
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
PCINT3
PCINT2
PCINT1
PCINT0
R/W
R/W
R/W
R/W
0
0
0
0
PCMSK2
PCMSK1
PCMSK0
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