ATmega168A Atmel Corporation, ATmega168A Datasheet - Page 162

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ATmega168A

Manufacturer Part Number
ATmega168A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168A

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Note:
Table 18-7
rect PWM mode.
Table 18-7.
COM2B1
0
0
1
1
Note:
• Bits 3, 2 – Reserved
These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read
as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
Table 18-8.
Mode
0
1
2
3
4
5
6
7
Notes:
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See
Mode” on page 154
for more details.
shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
Compare Output Mode, Phase Correct PWM Mode
COM2B0
Description
0
Normal port operation, OC2B disconnected.
1
Reserved
Clear OC2B on Compare Match when up-counting. Set OC2B on
0
Compare Match when down-counting.
Set OC2B on Compare Match when up-counting. Clear OC2B on
1
Compare Match when down-counting.
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
page 154
for more details.
Table
18-8. Modes of operation supported by the Timer/Counter
Waveform Generation Mode Bit Description
Timer/Counter
Mode of
WGM2
WGM1
WGM0
Operation
0
0
0
Normal
PWM, Phase
0
0
1
Correct
0
1
0
CTC
0
1
1
Fast PWM
1
0
0
Reserved
PWM, Phase
1
0
1
Correct
1
1
0
Reserved
1
1
1
Fast PWM
1. MAX= 0xFF
2. BOTTOM= 0x00
”Phase Correct PWM
(1)
”Phase Correct PWM Mode” on
”Modes of Operation” on page
151).
Update of
TOP
OCRx at
0xFF
Immediate
0xFF
TOP
OCRA
Immediate
0xFF
BOTTOM
OCRA
TOP
OCRA
BOTTOM
TOV Flag
(1)(2)
Set on
MAX
BOTTOM
MAX
MAX
BOTTOM
TOP
162

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