ATmega168A

Manufacturer Part NumberATmega168A
ManufacturerAtmel Corporation
ATmega168A datasheets
 


Specifications of ATmega168A

Flash (kbytes)16 KbytesPin Count32
Max. Operating Frequency20 MHzCpu8-bit AVR
# Of Touch Channels16Hardware Qtouch AcquisitionNo
Max I/o Pins23Ext Interrupts24
Usb SpeedNoUsb InterfaceNo
Spi2Twi (i2c)1
Uart1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorYes
Crypto EngineNoSram (kbytes)1
Eeprom (bytes)512Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers3Output Compare Channels6
Input Capture Channels1Pwm Channels6
32khz RtcYesCalibrated Rc OscillatorYes
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Page 98/567

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The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Out-
put Compare interrupt request.
15.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
15.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
15-2
shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
count
direction
clear
clk
top
bottom
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
”Using the Output Compare Unit” on page 125
”Timer/Counter0 and Timer/Counter1 Prescalers” on page
DATA BUS
count
clear
TCNTn
direction
bottom
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Tn
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
). clk
can be generated from an external or internal clock source,
T0
T0
is present or not. A CPU write overrides (has priority over) all counter clear or
T0
for details. The compare match
143.
TOVn
(Int.Req.)
Clock Select
Edge
Detector
clk
Tn
Control Logic
( From Prescaler )
top
in the following.
T0
).
T0
Figure
Tn
98