ATmega168A

Manufacturer Part NumberATmega168A
ManufacturerAtmel Corporation
ATmega168A datasheets
 

Specifications of ATmega168A

Flash (kbytes)16 KbytesPin Count32
Max. Operating Frequency20 MHzCpu8-bit AVR
# Of Touch Channels16Hardware Qtouch AcquisitionNo
Max I/o Pins23Ext Interrupts24
Usb SpeedNoUsb InterfaceNo
Spi2Twi (i2c)1
Uart1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorYes
Crypto EngineNoSram (kbytes)1
Eeprom (bytes)512Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers3Output Compare Channels6
Input Capture Channels1Pwm Channels6
32khz RtcYesCalibrated Rc OscillatorYes
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Figure 22-11. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-
mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the
status code in TWSR will be 0x08 (see
transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-
ing value to TWCR:
TWCR
value
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
TWCR
value
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
Device 1
Device 2
Device 3
MASTER
SLAVE
TRANSMITTER
RECEIVER
SDA
SCL
TWINT
TWEA
TWSTA
1
X
1
Table
TWINT
TWEA
TWSTA
1
X
0
Table
22-2.
TWINT
TWEA
TWSTA
1
X
0
TWINT
TWEA
TWSTA
1
X
0
TWINT
TWEA
TWSTA
1
X
1
V
CC
........
Device n
R1
R2
TWSTO
TWWC
TWEN
0
X
1
22-2). In order to enter MT mode, SLA+W must be
TWSTO
TWWC
TWEN
0
X
1
TWSTO
TWWC
TWEN
0
X
1
TWSTO
TWWC
TWEN
1
X
1
TWSTO
TWWC
TWEN
0
X
1
TWIE
0
X
TWIE
0
X
TWIE
0
X
TWIE
0
X
TWIE
0
X
230