ATmega256RZAV Atmel Corporation, ATmega256RZAV Datasheet - Page 136

• Manufacturer Part Number: ATmega256RZAV
• Manufacturer: Atmel Corporation

Specifications of ATmega256RZAV

• Flash (kbytes): 256 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
17.1
17.2
2549N–AVR–05/11
Features
Overview
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
the actual placement of I/O pins, see
“Pinout ATmega1281/2561” on page
pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the
ister Description” on page
The Power Reduction Timer/Counter1 bit, PRTIM1, in
page 56
The Power Reduction Timer/Counter3 bit, PRTIM3, in
page 57
The Power Reduction Timer/Counter4 bit, PRTIM4, in
page 57
The Power Reduction Timer/Counter5 bit, PRTIM5, in
page 57
Timer/Counter4 and Timer/Counter5 only have full functionality in the ATmega640/1280/2560.
Input capture and output compare are not available in the ATmega1281/2561.
True 16-bit Design (that is, allows 16-bit PWM)
Three independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Twenty independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,
OCF3B, OCF3C, ICF3, TOV4, OCF4A, OCF4B, OCF4C, ICF4, TOV5, OCF5A, OCF5B, OCF5C and
ICF5)
must be written to zero to enable Timer/Counter1 module.
must be written to zero to enable Timer/Counter3 module.
must be written to zero to enable Timer/Counter4 module.
must be written to zero to enable Timer/Counter5 module.
158.
ATmega640/1280/1281/2560/2561
4. CPU accessible I/O Registers, including I/O bits and I/O
“TQFP-pinout ATmega640/1280/2560” on page 2
“PRR0 – Power Reduction Register 0” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
Figure 17-1 on page
137. For
“Reg-
and
136