ATmega256RZAV Atmel Corporation, ATmega256RZAV Datasheet - Page 268
ATmega256RZAV
Manufacturer Part Number
ATmega256RZAV
Description
Manufacturer
Atmel Corporation
Specifications of ATmega256RZAV
Flash (kbytes)
256 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
Available stocks
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ATmega256RZAV-8MU
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24.9.3
24.9.4
2549N–AVR–05/11
TWSR – TWI Status Register
TWDR – TWI Data Register
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-
vated for as long as the TWINT Flag is high.
• Bits 7:3 – TWS: TWI Status
These five bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from TWSR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-
caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 24-7.
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
Bit
(0xB9)
Read/Write
Initial Value
Bit
(0xBB)
Read/Write
Initial Value
TWPS1
0
0
1
1
TWI Bit Rate Prescaler
TWS7
TWD7
R/W
R
7
1
7
1
TWS6
TWD6
R/W
“Bit Rate Generator Unit” on page
TWPS0
0
1
0
1
R
6
1
6
1
ATmega640/1280/1281/2560/2561
TWD5
TWS5
R/W
R
5
1
5
1
TWD4
TWS4
R/W
R
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWS3
R/W
R
3
1
3
1
247. The value of TWPS1:0 is used
TWD2
R/W
R
2
–
0
2
1
TWPS1
TWD1
R/W
R/W
1
0
1
1
TWPS0
TWD0
R/W
R/W
0
0
0
1
TWSR
TWDR
268
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